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How to manage the group and ungroup in synthesis ?

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u24c02

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Hello?

As I know, the ungroup command makes that one or all level unravel in the Design Compiler.
If I do ungroup then that level is unraveled at all, and this is making difficult to ECO.
So in my experience, generally, this command doesn't use.

But as I know DC_Ultra support ungroup by defaults. WHY?


Is there any good method during consider to ungroup and ECO in synthesis?
 
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