How to make analysis over parasitic devices so I can change the layout to produce expected simulation

[Awalluddin]

Hi, I design my circuit which is a mux 2-1 using Synopsys custom compiler. So I done the design flow first simulation continue with layout design drc, lvs and lpe. both drc and lvs are pass. However , when I do post layout simulation using config file, the sim is different then what I got from pre-sim. What I mean by different is not delay by few mili sec but like the output dont reach 1.2 V when it should be. So I tried to extract only R, C and RC separately. The result shows that it is fine if I just include only resistance devices only instead of C or RC. So here I figured out that the culprit here is the capacitance devices. The problem is how should I use this information which is the capacitance value from the extraction so I can change the layout design. What type of method or tools should I use. If there is any reading resources please recommend to me.

 

[timof]

Do you mean, that R-only extraction shows good results for post-layout simulation, while C-only and RC extractions show this problem?
Does your output voltage reach steady-state that is below an expected value of 1.2V, or does it not have time to reach the steady-state?

 

[dick_freebird]

I first recommend (if the layout is of manageable size) that you
open the av_extracted view, turn off all but instance/dwg layer,
select all and wade through the list of pcapacitors looking for
values large enough to matter. This will be "situational". You
might like to rerun extraction with a series of minimum-C values
(ignore, below) set and see where misbehavior rolls on, this
can clue you in to a range of C that has effect and narrow
your searching.

If you can (cross-)probe nets on the extracted view you may
be able to determine which ones are affected to cause your
issue. Then you can select devices for net, go to extracted view
and select nets for device, and see where the intersection is
physically.

It may be that the circuit contains bad art, such that any
capacitance at all will ruin performance. Such as (say) a soft
start whose charging current is not right, really just pullup
FET leakage and 10fF will kill you while 10aF looks "OK".
Rolling through minimum-C-extract-threshold might be good
for this kind of shotgun search for sort spots.