Hi, I design my circuit which is a mux 2-1 using Synopsys custom compiler. So I done the design flow first simulation continue with layout design drc, lvs and lpe. both drc and lvs are pass. However , when I do post layout simulation using config file, the sim is different then what I got from pre-sim. What I mean by different is not delay by few mili sec but like the output dont reach 1.2 V when it should be. So I tried to extract only R, C and RC separately. The result shows that it is fine if I just include only resistance devices only instead of C or RC. So here I figured out that the culprit here is the capacitance devices. The problem is how should I use this information which is the capacitance value from the extraction so I can change the layout design. What type of method or tools should I use. If there is any reading resources please recommend to me.