How to make a synthesizer use only specific gates in a design ?

[eladla]

Hi,
I am synthesizing some verilog code I wrote and want the synthesizer to only use specific gates in the design, NAND2/3, NOR2/3, NXOR2, INV and DFF.

Is there any way to do this?
I have two tools at my disposal: Leonardo spectrum and synopsys Synplify.

Thanks!

 

[Jack// ani]

Re: Limit gate use

Which device are you targeting?

Like in case of Xilinx FPGAs you can instantiate those gates from UniSim library to be sure only they are used by your synthesis tool.

 

[eladla]

Re: Limit gate use

I'm designing for an ASIC on the Leonardo side
and for a yet undetermined Altera device on the Synopsys.

Help me! Please!