how to make a lookup table in vhdl

[ahmedomar_2000]

i need to use this code ,i post just a small part , it is a very long values , so i need a help in how to use these values which appear below in my code in a lookup table ( ram or rom ),


if (outputt<=x"0e00" and outputt>=x"0d7a")then
output1<=x"0012";
-----------------------------------------------
elsif (outputt<=x"0d79" and outputt>=x"0ccd")then
output1<=x"0013";
-------------------------------------------
elsif (outputt<=x"0ccc" and outputt>=x"0c31")then
output1<=x"0014";
-------------------------------------------
elsif (outputt<=x"0c30" and outputt>=x"0ba3")then
output1<=x"0015";
-------------------------------------------
elsif (outputt<=x"0ba2" and outputt>=x"0b22")then
output1<=x"0016";
-------------------------------------------
elsif (outputt<=x"0b21" and outputt>=x"0aab")then
output1<=x"0017";
-------------------------------------------
elsif (outputt<=x"0aaa" and outputt>=x"0a3e")then
output1<=x"0018";
-------------------------------------------
elsif (outputt<=x"0a3d" and outputt>=x"09d9")then
output1<=x"0019";
-------------------------------------------

 

[FvM]

With suitable wrapping (e.g. placed in a clock synchronous process) a HDL compiler will probably accept the code as ROM description. You can use it in an initialization function.

As coded, you are are describing a 64k x 16 Bit ROM (1 Mbit, quite large). Is that what you want to achieve?

 

[ahmedomar_2000]

yes ,i want that

 

[Mina Magdy]

it is better to make it with (case) and at the end make when other to avoid latches as i think.

example

mux:PROCESS(s0, s1, in0, in1, in2, in3)
  VARIABLE  sel  :  STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
  sel := s1 & s0;   -- concatenate s1 and s0  

  CASE sel IS
    WHEN  "00"  =>  output <= in0;
    WHEN  "01"  =>  output <= in1;
    WHEN  "10"  =>  output <= in2;
    WHEN  "11"  =>  output <= in3;
    WHEN OTHERS =>  output <= 'X';
  END CASE;

END PROCESS mux;
  
END case_example;

 

[permute]

declare a type (in a package):

type my_lut_type is array (natural range <>) of std_logic_vector(16-1 downto 0);

and declare a huge constant within:

constant my_lut : my_lut_type(0 to 2**16 - 1) := ( x"0000", ... x"FFFF");

Or, if data permits, write a function that can generate it:

function make_my_lut return my_lut_type is
  variable return_lut : my_lut_type(0 to 2**16 - 1);
begin
  for idx in return_lut'range loop
    return_lut(idx) := <your code here>;
  end loop;
  return return_lut;
end function;

I think that is the correct syntax for a function of 0 arguments at least.

constant MY_LUT : my_lut_type(0 to 2**16 - 1) := make_my_lut();

Once this is done, you can use it in your code:

-- in a clocked process for BRAM implementations
x <= MY_LUT(integer_index);

You would need to make sure the index is an integer. Just keep in mind that for this size, each independent access to the constant will create a new ROM in hardware. Likewise, if you have async accesses to the ROM, you will end up inferring distributed ROM, which will use most/all/overmap the FPGA. Finally, you should not use async resets on the control lines to the ROM (including address), at least on Xilinx FPGAs. This is because of appnotes that say the BRAMs can become corrupted if the setup/hold of the address/en lines are not met even when not writing.

 

[YEAR_]

I know that Altera QUARTUS II and Xilinix WEB pack provide wizards to construct RAM or ROM blocks. synchronous memory operations guarantee safer implementation. a little bit of reading on HDL code to resource mapping will be helpful.