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# How to make a current mode buck converter stable?

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#### rockycheng

##### Member level 5
buck converter current mode

Hello everyone,

I have some confusions about the stability of current-mode buck converter.

Question 1: In current mode, does the control to output transfer function fall at 20 or 40dB per decade? If it's 20dB/decade, why do we have to compensate the error amplifier (to add a zero)?

Question 2: In order to eliminate the "sub-harmonic oscillation", do I just make the compensation ramp slope mc larger than one half of m2? Is there any upper limit of mc?

I've made a current mode converter, but there seem to be problems. When I make the duty cycle larger than 0.5, it's not stable (please see the figure). When duty cycle is less than 0.5, it is ok.
Do you think what kind of problem is this? BTW, I haven't consider the loop stability very carefully, since I'm not quite understand it. It would be very nice if you help me out! Thank you!

#### electronrancher

buck converter power stage layout

1) Current mode has one pole due to the load and Cout, and another pole due to the error amp (integrator). Therefore you do need a zero to cross at -20dB/decade.
2) M2 is the rate at which the inductor downslope falls, basically equal to Vout/L. You have to restrict either your Vout or your L or you end up thinking this quantity could be very large which means your slope comp ramp needs to be very large. However, in the case of low inductor downslope (say L is large) if you have too much slope comp your converter will act like a voltage mode, giving back the double pole at LC and will not be stable. A good rule of thumb is to put half your current limit's worth of slope comp.

In your graph, you get big pulse/little pulse which is characteristic of SHO. I also supsect your compensation is wrong, as the SHO starts to fade at 40us, but comes back due to another perturbation which is probably due to loop instability.

In order to verify that your slope comp is OK, run an open loop sim where you just drive comp with a fixed voltage, you should settle into steady state with no SHO.

### rockycheng

Points: 2

#### huojinsi

##### Full Member level 5
current mode buck converter

At present, i am studying the current mode control in switch power. Give u a tutorial, hope it help u!

### rockycheng

Points: 2

#### rockycheng

##### Member level 5

Electronrancher,

Thank you for your reply! What is "SHO"? I've used a fixed voltage instead of the ramp compensation. It's not stable either. I think it's reasonable, since a fixed voltage seems equal to that without compensation. But maybe I was wrong, I didn't run open loop sim as you said. I don't know how.

huojinsi,

Thank you for the paper. I've read through it. I'm interested in Page 6. It says "above 1/6 to 2/3 of the switching frequency, the control to output transfer function starts to fall at a -2 slope again", does that mean we should make the unity gain frequency below 1/6 of the switching frequency? Or the loop will not be stable. But what is the specific way to measure that corner frequency between -1 and -2 slope? And, I've no idea how to locate the unity gain frequency accurately.

#### VVV

buck converter slope compensation current mode

In current-mode bucks the slope is -1. However, need the zero since your erro amp has a pole, which is required to keep the low frequency gain high.

Adding too much slope compensation will make the converter operate more like a voltage mod one, instead of current mode.

Suharmonic socillation (SHO) means the duration of the pulses alternates, one longer, the next shorter, and so on, so it's an oscillation at half the switching frequency. Since it occurs at duty-cycles over 50%, the fact that your converter works OK up to that point would indicate that SHO occurs.

But the error amplifier output you are showing really looks like the loop breaks into oscillation, too. Perhaps it is some parasitic coupling, due to the higher currents; after all, when your duty-cycle reaches 50%, the current is higher, since the input voltage is low.
I would check the layout very carefully.

Measuring the loop is done with a gain-phase analyzer, such as the HP4192A, an expensive piece of equipment. This is done with a small resistor (10-22 ohm) in series with your top divider resistor. The signal from the anlyzer is aplied through a transformer right across this small resistor. The signals are the measured with respect to GND at each end of this resistor: the power supply output side is the TEST channel and the other side is the REF channel. The analyzer then does the 20*log(TEST/REF) [dB] for you and also measures the phase difference. This effectively allows you to measure the "open loop" , although the loop is closed, allowing the power supply to function normally. (Remember, this resistor is small and the signals are in the tens of mV range).

The so-called crossover frequency is that where the gain is 0dB. You find that by moving the cursor of the instrument. At that point you read the "phase margin" on the second curve.

### rockycheng

Points: 2

#### rockycheng

##### Member level 5
current mode buck converter oscillations

Thank you very much VVV!

#### zenisle

##### Full Member level 2

would check the layout very carefully

#### electronrancher

how to measure current in buck converter

This is only simulation, so it's probably not a layout issue - yet. You're right that SHO = Subharmonic Oscillation. It will be difficult to see whether you loop is stable if your current sense loop is not stable. You should really try to run your switch, current sense, and pwm comparator together in a loop.

When I do this, I drive the "COMP" node with a fixed voltage to get a known current limit - let's say if my power Gm (Ratio of cycle current to Comp voltage) is 3A/V, and I set COMP to 0.5v, I would expect 1.5A per cycle.

I build a schematic with my oscillator, current sense amp, pwm comparator, and power stage. I set it up to drive a nominal load (usually a resistor or current source sized so I know the circuit will be operating in CCM) and run it without the error amp until it reaches steady state. The sim is usually pretty fast since it's not the full chip, and it easily allows you to verify that the current sense loop is stable.

Now that you are sure the current loop is stable, you need to compensate the outer (voltage) loop with a standard compensation network. This you must calculate or use mathcad for - it's more work to do trial and error since full chip sims may take days depending on their size.

You can always overdamp the converter, using a large compensation cap so you are sure it will be stable, but it will also be slow to reach steady state so it's usually better to calculate it out and just do it right the first time.

Is your error amp a GM or op amp? What's the compensation you're using? What's the power GM? and do you have a current limit - what is it?

All in all, you
1) Need a slope comp signal. Making a copy of the oscillator ramp is the standard way of doing this.

2) Need to compensate your converter. If you only have one zero on the comp network, you can add a second zero by placing a cap across the TOP feedback resistor - fz = 1/(2pi*R*C). I think this will help.

#### rockycheng

##### Member level 5
buck converter current control loop stability

Thanks electronrancher! This is really helpful! Now the loop becomes stable, after adjusting the compensation of error amp. Your suggestion is very good!

#### rockycheng

##### Member level 5
current mode buck compensation network

When the switch frequency is reduced a little (from 500kHz to 300kHz), the inductor current looks strange. I'm not sure if it's stable. The "ripple" of the inductor current and Veao are all very large. Please see the "300kHz" figure. I also post the "500kHz" one, which I think is stable.

#### huojinsi

##### Full Member level 5
buck converter current limit

Hi rockycheng
huojinsi,
Thank you for the paper. I've read through it. I'm interested in Page 6. It says "above 1/6 to 2/3 of the switching frequency, the control to output transfer function starts to fall at a -2 slope again", does that mean we should make the unity gain frequency below 1/6 of the switching frequency? Or the loop will not be stable. But what is the specific way to measure that corner frequency between -1 and -2 slope? And, I've no idea how to locate the unity gain frequency accurately.

From up many posts, i think u do have the solution of ur doubt. I feel VVV is a person who do a deep research on switch power. u may directly consult VVV if u will have any doubt in the future.

#### VVV

how to make a buck converter

The inductor current does not look strange to me, just the ripple is indeed rather high. But that is simply because the inductor is too low for the output current and the switching frequency you are running at. Inductor current ripple should be kept at about 30% of the nominal output current, although this is not a requirement. You just need to make sure the ripple current of the output cap is not exceeded and the inductor does not overheat. Also, you will probably need lower ESR output caps, to keep the voltage ripple within spec.
I think in your case it is more than 30%, but again, this should not be a problem, just check the items I mentioned.

The error amp voltage seems to show some ripple, but it does not look like oscillation to me, since it is at the switching frequency. What I suspect is that the layout is not done properly and somehow you are picking up some voltage spikes generated by transistor drain current.

But it can also be, more likely, generated by the gate drive current, which is normal, since the gate current also goes through the sense resistor. And peak gate currents are short, but of high amplitude, so the voltage due to them can be seen across the sense resistor.

To check that, connect one channel of the scope to the gate of the transistor and the other at the Vsense+Vramp. Check if the falling edge of the gate drive signal coincides with the negative-going spike right at the top of the Vsense+Vramp. If it does, then you are simply seeing the gate current as the transistor is being turned off, which is normal.

The ripple at the Vea output seems strange, given that your loop is much slower than the switching frequency, therefore, I wonder if it's not a a case of improper grounding, or improper measurement. That ripple looks much like the output ripple, which would indicate that the error amp is not properly compensated, which I find hard to believe, since it seems stable, or it could be that the ground point was not chosen properly. I mean, even the scope probe ground may have been connected to the wrong point. When you are measuring the error amp output, make sure the GND of the probe is near the error amp ground, not some point where you have power components connected to.

#### rockycheng

##### Member level 5
current mode buck-converter

VVV, thank you very much! I have a question about a general concept: In steady state, should the inductor current reach the peak every cycle? In the 500kHz case, it is. But as you can see, the peak occurs every two cycles in the 300kHz case. Is this normal?

BTW, I'm just doing the schematic-level simulation. So it's not layout problem or testing mistake.

#### hylas

##### Junior Member level 3

It is not normal for your 300kHz case. There is subharmonic oscillation. You may try to adjust the slope compensation to correct the problem. Inductor current profile should be the same for every switching cycle in steady state.

#### rockycheng

##### Member level 5
current mode converter

Thanks hylas! I agree with you. I'll check the slope compensation again.

#### VVV

current mode too much slope compensation

If something is different every other cycle, then that indicates subharmonic oscillation, so the slope compensation must be revisited.

roy mathew

Points: 2