how to make 4 bits adder to output 5 bits ?

[gunnerunbeaten]

when i write code below :

library IEEE;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
.....
signal stage1 : unsigned (63 downto 0);
signal stage2 : unsigned (39 downto 0);
...
[COLOR="#FF0000"]stage2(4 downto 0) <= stage1(7 downto 4) + stage1(3 downto 0) ;[/COLOR]

after synthesis , there is error : " Target slice is 5 elements ; value is 4 elements ". Then i change inputs to 5 elements, but the timing is increase.
in verilog 4 bits + 4 bits => 5 bits is OK, how to do that in VHDL?

 

[Debdut]

You can try this:
stage2(4 downto 0) <= ('0' & stage1(7 downto 4)) + ('0' & stage1(3 downto 0));

 

[std_match]

Use "resize" on one of the operands, to make it the same size as the result:

stage2(4 downto 0) <= resize(stage1(7 downto 4), 5) + stage1(3 downto 0);

 

[TrickyDicky]

You can try this:
stage2(4 downto 0) <= ('0' & stage1(7 downto 4)) + ('0' & stage1(3 downto 0));

This is fine for the OP's unsigned example, but std_match's example will work for signed and unsigned types.

 

[gunnerunbeaten]

Use "resize" on one of the operands, to make it the same size as the result:

stage2(4 downto 0) <= resize(stage1(7 downto 4), 5) + stage1(3 downto 0);

how about : 1 bit + 1 bit => 2 bits. when synthesis , i see error when " 1 bit + 1 bit " ????

- - - Updated - - -

This is fine for the OP's unsigned example, but std_match's example will work for signed and unsigned types.

how about : 1 bit + 1 bit => 2 bits. when synthesis , i see error when " 1 bit + 1 bit " ????

 

[TrickyDicky]

Show the code that has the problem. Std_match's example will work for all sizes.

 

[std_match]

how about : 1 bit + 1 bit => 2 bits. when synthesis , i see error when " 1 bit + 1 bit " ????

No problem, if you use vectors of length 1, like "stage1(4 downto 4)".
It doesn't work for single bits, like "stage1(4)".

 

[gunnerunbeaten]

No problem, if you use vectors of length 1, like "stage1(4 downto 4)".
It doesn't work for single bits, like "stage1(4)".

in verilog , this code :

stage1[3:0] <= stage0[7] + stage0[6] + stage0[5] + stage0[4] + stage0[3] + stage0[2] + stage0[1] + stage0[0] ;

have no problem when synthesis, but when running in FPGA , the result is fail.
so I change this to VHDL :

stage1(3 downto 0) <=     stage0(7) +   stage0(6) +   stage0(5)  ;

the synthesis is error : "found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+""

your mean i have to do that ???

stage1(3 downto 0) <=     resize (stage0(7 downto 7),4) +   resize (stage0(6 downto 6),4) +   resize (stage0(5 downto 5),4)

 

[TrickyDicky]

Yes. Remember VHDL has a strong typing system.

So
signal a : unsigned(7 downto 0);

a is an array of std_logic

a(4) is a std_logic type. It is not an array. There are no arithmetic functions for std_logic type.
a(4 downto 4) is an unsigned type of length 1. hence you can do arithmatic on it.

 

[gunnerunbeaten]

Yes. Remember VHDL has a strong typing system.

So
signal a : unsigned(7 downto 0);

a is an array of std_logic

a(4) is a std_logic type. It is not an array. There are no arithmetic functions for std_logic type.
a(4 downto 4) is an unsigned type of length 1. hence you can do arithmatic on it.

Thank you so much !

 

[std_match]

It is enough to use "resize" on one of the operands:

stage1(3 downto 0) <= resize(stage0(7 downto 7), 4) + stage0(6 downto 6) + stage0(5 downto 5);

 

[gunnerunbeaten]

It is enough to use "resize" on one of the operands:

stage1(3 downto 0) <= resize(stage0(7 downto 7), 4) + stage0(6 downto 6) + stage0(5 downto 5);

std_match ,How about Resize in verilog ??