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When switch SW1 is opened C1 should discharge quickly to prepare inrush circuit for new start. For that purpos serves diode D1. It bypasses resistor R2 for discharge current of C1. Discharge current flows through R1, load and D1.
What about the below idea?
That is, it is for the gate voltage to be fallen slowy(in P-FET) by using some large capacitor to the gate pin. Can this method be harmful to the FET with respect to the Electrical Stress ?
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