How to layout the mos capacitor to decrease gate leakage ?

[xihuwang]

Re: How to layout the mos capacitor to decrease gate leakage

Hi:
I am working on a pll . When the leakage current of the capacitor
of the LPF above 100nA, the pll 's performance will not be accepted.
So, I want to know ：
1. how much are the gate leakage for a 50pF mos cap in 0.13um ，0.25um ，0.35um process
2. How to layout the mos cap to decrease the leakage? Does decrease the unit
cap 's area make sense ?

Added after 2 minutes:

Any help docs ?

Thanks forwards !

 

[erikl]

Re: How to layout the mos capacitor to decrease gate leakage

1. how much are the gate leakage for a 50pF mos cap in 0.13um，0.25um ，0.35um process

Gate leakage depends on the gate dielectric material used (SiO2, SiON, high-k dielectrics ...), on its thickness, the electric field strength in the material, on temperature, and on the gate area, of course. Leakage current through dielectric insulators is not necessarily only due to Ohm's law, but may be greatly increased by avalanche mechanism (near electrical breakdown field strength) or by tunnel effect (for such thin layers present as gate dielectrics).

Leakage values are process-dependent, and you should get distinct unit area values for well-defined PVT conditions from the process foundry.

2. How to layout the mos cap to decrease the leakage?
Does decrease the unitcap 's area make sense ?

Not necessarily, if this would mean increasing the voltage at the same time, and area, of course. The best you can do is stay far enough away from breakdown and tunneling mechanisms, i.e. - if possible - use the minimum DC voltage which is necessary for inversion of the MOS cap, i.e. just a bit more than Vth. If this can be done, you may use the densiest technology and thus get the lowest cap area without trading for leakage current.

... above 100nA, the pll 's performance will not be accepted.

For normal conditions - i.e. V(cap,DC)≈Vth and commercial/industrial temperature range, the leakage current of a 50pF mos cap should be far below this 100nA limit, more or less in the range of fA or max. pA (for max. temperature).

Any help docs ?

PDK from your foundry!

 

[leo_o2]

Use thick gate oxide device for cap to reduce the gate leakage.