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how to layout a guardring?

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leohart

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I was always thinking guardring is just a n+ vdd tieup ring for transistors in nwell and p+ gnd tiedown for transistors in psub.And if we need more latchup immunity,just use p+ gnd tiedown ring and a n+ vdd tieup nwell ring around,this is called double guardring.But this is only for nmos,how to do double guard ring for pmos in nwell?

But Art of analog layout said guard ring for nmos should use n+ guardring and it is tied to gnd??
 

leohart said:
I was always thinking guardring is just a n+ vdd tieup ring for transistors in nwell and p+ gnd tiedown for transistors in psub.And if we need more latchup immunity,just use p+ gnd tiedown ring and a n+ vdd tieup nwell ring around,this is called double guardring.But this is only for nmos,how to do double guard ring for pmos in nwell?

But Art of analog layout said guard ring for nmos should use n+ guardring and it is tied to gnd??



the author of the book must be kidding if he meant that way....:D
 

N+ tied to ground guardring (substrate tap) is also possible for NMOS. This type of guard ring is to help reducing latchup. HOwever, Nwell tied to VDD guard ring is also possible for NMOS due to its deep penetrating into the substrate.
 

inside nwell put n guard ring and outside nwell put p guard ring
 

Art of analog layout must mean: for NMOS, you can have a P+ ring (body connection) connecting to ground first and outside the P+ring, you need to add N+ring round the P+ring and connect it to VDD.
For PMOS, you need to have a N+ ring at the edge of the Nwell for body contact and outside the Nwell, you need to add a P+ ring. It is double guard ring for PMOS.
 

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