hey there ,
so in my code i need to know how many times a while loop was excuted (i don't know the number of iteration in advance and i should know it in a division algorithm )
how to know the value of I outside the process in the following example ?
PHP:
process (r,b)
variable I :integer :=0 ;
begin
WHILE (x > b) LOOP
x <= r+b ;
I:=I+1 ;
END LOOP ;
end process;
3 comments after a casual glance.....
1. You are doing a comparison between x and b but have not included x in the sensitivity list.
2. Avoid using 'while' loop (if this piece is used for non-synth part of the design, then ok with while loop)
3. I am assuming 'I' is storing the no. of iterations. So declare it as signal and then use it accordingly if you want to use it in another process.
3 comments after a casual glance.....
1. You are doing a comparison between x and b but have not included x in the sensitivity list.
2. Avoid using 'while' loop (if this piece is used for non-synth part of the design, then ok with while loop)
3. I am assuming 'I' is storing the no. of iterations. So declare it as signal and then use it accordingly if you want to use it in another process.
thanks a lot,i'm sorry for making such horrible mistakes,i need to synthesis this code,i'm going to do a number of repeated substraction until i reach a certain condition (for example a>b ..) so can you give me a suggestion in whish structure should i use to do that,knowing that i'm dealing with signed numbers thanks a looot !
thanks a lot,i'm sorry for making such horrible mistakes,i need to synthesis this code,i'm going to do a number of repeated substraction until i reach a certain condition (for example a>b ..) so can you give me a suggestion in whish structure should i use to do that,knowing that i'm dealing with signed numbers thanks a looot !
The code can't be synthesized anyway due to unconstraint iteration count.
I presume it's based on the popular misunderstanding that an iteration loop defines a sequence in time. But it's only sequentially executed in simulation. In synthesis it instantiates parallel logic. Because the iteration count can't be determined at compile time, it's dropping a synthesis error.
In cases where you actually want to generate parallel logic by an iteration construct, the compiler must know how many instances. A for next loop will tell this by its fixed range.
As ads-ee explained, a sequential divider will use a loop counter and a clock. Under circumstances you can define a parallel divider by an iteration construct. But it would be better generated in a hierarchical structural description.
can you recommand any book or tutorials that can help me understand how a design work on hardware ? when it can be synthesizable and when not and why ? i feel like it's hard to write VHDL with my basic electronics knowlege
i'm so grateful,thanks for your answers
regards jojo