How to know the number of gates used in a design ?

[pstar]

Number Of Gates!?

Hi All,

I am using Digilent Spartan-3 board with Xilinx Webpack 6.3i. In my design I used:

-16x16 multiplier
-32-bit comparator less
-32-bit comparator greater
-32-bit comparator equal
-32-bit adder

Since I just used <,>,=,+, and * in my verilog I don't know what type of design webpack used for each of these operations.

I need to know exactly how many AND,OR,XOR,... gate used in this design so I need to know how many gate it used for each operation. But I couldn't finf this numbers anywhere in reports or manual.

If you guys know where I can find these number of gates it will be a very useful help. Or if you already knew the design of each of these (that Xilinx webpack used)and number of gates for each one could you please post it here. Any link to refrence or PDF library that contains this information also can be very helpful.

Thank so much.

Take care,
Pouya

 

[echo47]

Number Of Gates!?

Equivalent gates count is usually not interesting for an FPGA. Do you need that value for a military reliability calculation?

The Xilinx ngdbuild utility outputs a design summary that includes the total equivalent gate count.

When I build an FPGA, I use a makefile that runs xst, ngc2edif, ngdbuild, map, par, trce, and bitgen.

 

[pisoiu]

Number Of Gates!?

Take a look in the map report (.mrp file) and synthesis report (.syr file). There you will find what you are looking for.

/pisoiu

 

[sp]

Re: Number Of Gates!?

Take a look in the map report (.mrp file) and synthesis report (.syr file). There you will find what you are looking for.

/pisoiu

could i ask how to do tht in altera max-plus II.....is it posible?...wad file/s will hav tht info...

quite interesting....