How to interface FLASH ADC with FPGA

[safiqul_03]

Hi,

I am trying to measure the RC time constant (exponential decay time) by FPGA. I have already done it by micro-controller with two comparators. But now, I want to do it by FPGA and want to use VHDL.

For that, I have choosed Flash ADC (MAX105) and FPGA - ACTEL ProASIC3E (A3PE1500). But, I have no idea how to interface between Flash ADC and FPGA. I need also the counter value that can count the time for each sample.

The RC time constant only 100 us.

Please help me to find out this! Thank you!

View attachment MAX105 [6 bit Flash ADC].pdf View attachment A3PE1500 [FPGA].pdf

 

[keerthipriyan_s]

refer xilinx form

 

[safiqul_03]

Hi,

Can anybody help me to give some idea how to interface Flash ADC with actel proAsic3 FPGA? Please.....

Hi,

I am trying to measure the RC time constant (exponential decay time) by FPGA. I have already done it by micro-controller with two comparators. But now, I want to do it by FPGA and want to use VHDL.

For that, I have choosed Flash ADC (MAX105) and FPGA - ACTEL ProASIC3E (A3PE1500). But, I have no idea how to interface between Flash ADC and FPGA. I need also the counter value that can count the time for each sample.

The RC time constant only 100 us.

Please help me to find out this! Thank you!

View attachment 62883View attachment 62884View attachment 62882

 

[mrflibble]

So what specific problem do you have? If you want generic answers to your generic question, then "you just connect some wires, write some FSM, and you're done!".

 

[safiqul_03]

Hi,
Thanks for your reply!

The flash ADC gives 8 bit parallel data with LVPECL/LVDS output. I need to connect to the 8 LVDS input of the FPGA and capture the counter value for each bit changes. I do not have idea how can I handle this parallel data by VHDL code. Would you please suggest me some VHDL code examples related to this?

The data rate for the ADC is 400Mhz, but my FPGA clock is 300 Mhz. So, How can I handle this? Would you please overview my flash adc data sheet (attached) and FPGA (attached) datasheet and advice me that the components are ok/not to measure this RC signal?

So what specific problem do you have? If you want generic answers to your generic question, then "you just connect some wires, write some FSM, and you're done!".

 

[FvM]

The ADC is a high speed device which requires sophisticated layout technique. I'm under the impression, that the analog circuit design as well as the FPGA interface implementation is far beyond your level of electronics knowledge. What's your point of measuring a 100 us time constant with a 6 Bit 400 MHz ADC? You'll achieve much more exact time constant measurements with a slower but higher resolution ADC.

 

[mrflibble]

Just by way of testing what kind of answer I should be giving ... you mention:

I need also the counter value that can count the time for each sample.

What kind of HDL code are you using for that now?

 

[safiqul_03]

Hi,

I want to use VHDL. And the question is....

1. I want to measure the RC time constant which is +/-100us by Flash ADC and FPGA
2. How to interface 8 bit parallal data (from Flash ADC) with FPGA by VHDL code
3. If the flash ADC data rate is greater than FPGA data rate than how can I handle this?


Thank you!

Just by way of testing what kind of answer I should be giving ... you mention:



What kind of HDL code are you using for that now?

 

[mrflibble]

Do you intend to use a ready made fpga development board for this? Or ... the ever popular beginner mistake "I Will Make My Own Board ^_^".

If a ready made board, which one? If the DIY ... please don't. Because if you have to ask things like "If the flash ADC data rate is greater than FPGA data rate than how can I handle this?" ... then see FvM's post.


Besides, as FvM points out this is probably not the best way to measure a simple RC constant. But what the hell, if you want to choose a certain implementation for whatever reason, go for it.

As for implementations that make sense, you're probably better of getting a good 24-bit ADC dev board, and work from there. I can recommend the ADS1258EVM (have one myself). At ~ 50 euro that is pretty awesome value for money IMO.

 

[safiqul_03]

Hi,
Thanks for your suggestion!

I am using ORSoC FPGA development board (**broken link removed**). I need the VHDL example code for communication between Flash ADC (8 bit parallal) and this FPGA.

Do you intend to use a ready made fpga development board for this? Or ... the ever popular beginner mistake "I Will Make My Own Board ^_^".

If a ready made board, which one? If the DIY ... please don't. Because if you have to ask things like "If the flash ADC data rate is greater than FPGA data rate than how can I handle this?" ... then see FvM's post.


Besides, as FvM points out this is probably not the best way to measure a simple RC constant. But what the hell, if you want to choose a certain implementation for whatever reason, go for it.

As for implementations that make sense, you're probably better of getting a good 24-bit ADC dev board, and work from there. I can recommend the ADS1258EVM (have one myself). At ~ 50 euro that is pretty awesome value for money IMO.

---------- Post added at 14:32 ---------- Previous post was at 14:17 ----------

Hi,
This RC time constant is temperature dependent. For each degree, the time constant changes only 5ns. And I need also the counter value for each triggering point of the comparator. That what I want to measure. If I use SAR ADC, I will not get the comparing level of the signal. And to get this, Flash ADC is the solution as I have understood. In the market, only 8 bit Flash ADC is available because it needs 2n-1 comparator.

The ADC is a high speed device which requires sophisticated layout technique. I'm under the impression, that the analog circuit design as well as the FPGA interface implementation is far beyond your level of electronics knowledge. What's your point of measuring a 100 us time constant with a 6 Bit 400 MHz ADC? You'll achieve much more exact time constant measurements with a slower but higher resolution ADC.

 

[mrflibble]

I think the hint FvM is trying to give you is that your chosen implementation might not be the most sensible.

If ALL you want is an RC constant ... why do you feel that you need such a fast flash dac. Yeah yeah SAR vs flashdac differences I understand, but that is besides the point.

If the waveform is a fair approximation of an exponential, and you have amplitude information, then you could do much better (and cheaper) with a fast comparator + TIC combo.

Lets put it another way... have you done a search for available techniques for this? If yes, what list of possible techniques do you have, and how the hell did you end up chosing the 6 bit flashdac option?

 

[FvM]

You told about a 8-Bit ADC, but the said MAX105 is only 6 Bit, and as I already mentioned, much too fast for a suitable entry level project. If you possibly have a ready-to-use hardware available, we can discuss, if it would be usable anyway. But you should be sure, that the setup has been working before and isn't just some remains from other's projects with unknown results.

Apart from the FPGA interface problem, you should take into account, that ADC voltage resolution can be traded against sampling rate when you want to measure RC time constants with a certain accuracy. You didn't tell yet a full specification, so I don't feel invited to guess about an optimal trade-off for your project. I just expect it at lower sampling rates for a 100 us RC time constant.

 

[joelby]

I don't think the ORSoC board will be suitable for interfacing with a 400 MHz serial ADC. It has not been designed for high speed serial communications and lacks a high speed I/O header. You will probably experience signal integrity and skew issues, which are difficult to debug. Trust me!

Also, I don't think the ADC is appropriate for your needs at all. 800 MSPS is probably much faster than what you need. 6-bit resolution may not be enough. Constructing a suitable circuit board for it will be quite expensive and will require a reasonable amount of high speed design experience to get right.

I'm not at all familiar with these parts, but it doesn't appear that they have any built-in high speed SERDES blocks. 300 MHz is almost certainly faster than what you would be able to achieve in fabric logic. From the Xilinx range, I would use a Spartan-6 FPGA, which has hardware SERDES.

 

[lucbra]

Just as a heads up - you wrote that you used a micro controller (see your first post) and two comparators. Why don't you take the same approach in the FPGA implementation? Use two comparators (each @ 5$ - and you'll get much for that price), connect them to your FPGA. With some easy counters and the comparators, you'll get pretty close...

 

[mrflibble]

Why don't you take the same approach in the FPGA implementation? Use two comparators (each @ 5$ - and you'll get much for that price), connect them to your FPGA. With some easy counters and the comparators, you'll get pretty close...

Agreed, that approach makes sense. And it's precisely what I meant with ...

If the waveform is a fair approximation of an exponential, and you have amplitude information, then you could do much better (and cheaper) with a fast comparator + TIC combo.

To be more precisely, the fast comparator + TIC combo == two comparators (one for the START condition, one for the STOP condition). And the TIC (Time Interval Counter) is a counter on the fpga that gives you the time difference between START and STOP conditions.

Depending on your resolution requirements you can choose various TIC implementations.
1) straight up binary counter, resolution = 1 clock period of fpga system clock. E.g 400 MHz clock ==> 2.5 ns resolution
2) staggered clocks. For example 4 phase locked clocks at 400 MHz, each shifted 90 degrees. ==> 625 ps resolution
3) get creative with a single SERDES. Serdes clock can be around 1 GHz ==> 1 ns resolution
4) multiple SERDES, similar to staggered clock approach. (I have NOT tested this particular approach in hardware)
5) tapped delay line, using the carry chain as delay elements. ==> 500 ps resolution for very poor implementation, ~ 10 ps for very good implementation. (That's all in ps rms, single shot).

If you just start out in fpga's then a staggered clock approach is easy enough, and without too much hassle can get you resolution under 1 ns. And as free bonus, with the staggered clock approach you get to deal with multiple clock domains and synchronization.

 

[safiqul_03]

Hi,
Would you please give me the example VHDL program for it? I do not have idea to use SERDES/staggered clocks.

Agreed, that approach makes sense. And it's precisely what I meant with ...



To be more precisely, the fast comparator + TIC combo == two comparators (one for the START condition, one for the STOP condition). And the TIC (Time Interval Counter) is a counter on the fpga that gives you the time difference between START and STOP conditions.

Depending on your resolution requirements you can choose various TIC implementations.
1) straight up binary counter, resolution = 1 clock period of fpga system clock. E.g 400 MHz clock ==> 2.5 ns resolution
2) staggered clocks. For example 4 phase locked clocks at 400 MHz, each shifted 90 degrees. ==> 625 ps resolution
3) get creative with a single SERDES. Serdes clock can be around 1 GHz ==> 1 ns resolution
4) multiple SERDES, similar to staggered clock approach. (I have NOT tested this particular approach in hardware)
5) tapped delay line, using the carry chain as delay elements. ==> 500 ps resolution for very poor implementation, ~ 10 ps for very good implementation. (That's all in ps rms, single shot).

If you just start out in fpga's then a staggered clock approach is easy enough, and without too much hassle can get you resolution under 1 ns. And as free bonus, with the staggered clock approach you get to deal with multiple clock domains and synchronization.

 

[mrflibble]

Hi,
Would you please give me the example VHDL program for it? I do not have idea to use SERDES/staggered clocks.

From previous post:

2) staggered clocks. For example 4 phase locked clocks at 400 MHz, each shifted 90 degrees

I'm sure you can manage to generate 4 clocks at 0, 90, 180 and 270 degrees. Besides, no habla vhdl senor.

 

[mrflibble]

To be slightly less vague ...

The staggered clocks are nothing more than say a 400 MHz clock (or whatever your fpga can handle), with 4 versions of it (0, 90, 180 and 270 degrees). You generate those using the PLL/DCM/whatever clocking resources in the fpga. But I am sure you found that out in the meantime by simply googling.

Then you sample your input signal using all these clocks. So you have 4 flip-flops, each clocked by the posedge of the 0,90,180,270 degree clock respectively. This way you have divided the 2.5 ns clock cycle into 4 even parts.

After that you have to decode the 4 bits. Which is done by 1) synchronizing to one clock domain and 2) simple case statement. Decoding becomes really simple if you can guarantee that you have max 1 transition in those 4 bits. Which will be the case for your application.