how to interface 128k parallel ram using 16 address lines

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yogikool

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hi all

I want to interface 128 k parallel ram to 8 bit uC using (A0 --A15)16 address lines.

is it possible ???

how to do it??

pl. help.
 

Re: how to interface 128k parallel ram using 16 address line

As 16 address lines can only address 64kB of memory .. A0-A15 .. you can use any other microcontroller's pin as A16 ..
In other words, before you attempt to read/write memory cells of the upper/lower 64kB bank set/clear that bit ..

For example, in 8051-40-pin-derivative you can use AD0-AD7 as A0-A7, P2-port as A8-A15 and P1.0 as A16, P1.1 as A17, P1.2 as A18, P1.3 as A19, .. and so on ..
In this way you are not limited to 64kB memories ..

Regards,
IanP
 

Re: how to interface 128k parallel ram using 16 address line

Please be sure NOT to load this RAM with code then try to run it from the RAM chip, as u will not be able to synchronize your Additional bits (page address) setup to the change of the Program Counter register.

This technique is only valid if u need to store some program data into this RAM.

Hope this helps.
 

Re: how to interface 128k parallel ram using 16 address line

Hi Yogokool,

There are a lot of ways to achieve this, this only one of many.

on1aag.

 

Re: how to interface 128k parallel ram using 16 address line

I think there's something missing in the above graph as it did nit mention the IO/M control line. Thus, how to knot this address is directed to a memory or I/O port?
 

Re: how to interface 128k parallel ram using 16 address line

CPU A0.... A15 ==> Ram1 A0....A15
CPU A0.... A15 ==> Ram2 A0....A15

Ram1 CS(active low) = NOT ((NOT Bank_Sel) AND Mem_Req)
Ram2 CS(active low) = NOT (Bank_Sel AND Mem_req)

Mem_req=(NOT Rd) OR (NOT Wr) may need some extra signals. (external memory access signals)

Bank_sel is a latchable pin.

(Rd and Wr active low)

Do Bank_sel=0 and after you can access to any address of Ram1
Do Bank_sel=1 and after you can access to any address of Ram2

This method work but all 64K for the ram access and not allow to coincide by other peripherals.
 

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