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How to Instantiate a VHDL entity in verilog module ?

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blooz

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How can we instantiate a VHDL entity inside a verilog module .I am using Active HDL..
 

Alexium

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You just have to instanciate module header that would be semantically the same as VHDL entity. When the VHDL module is added to project and you want to use it inside Verilog module, you simply imagine that VHDL component is written in Verilog and use it as if it actually is.
 

FboDigit

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And pray that there is no array in your VHDL code because verilog don't yet support array on inputs and outputs.
 

syedshan

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Yes Alexium is right, just treat your VHDL enitity declaration as if it is a verilog module declaration. and do the same instantiation as in for verilog modules.
 

eng.amr2009

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High there

If the VHDL component has generics, Does the generic mapping work inside a verilog module

simply MyFile.vhd is a generic VHDL entity instantiated inside MyTop.v ... Does the generic mapping of MyFile.vhd inside MyTop.v work ?


thanks in advance
 

ads_ee

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If the VHDL component has generics, Does the generic mapping work inside a verilog module

yes it works. I'm using this in a current project.

Just assign the generics as if they were parameters in a Verilog module.
 

FvM

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Some tools, e.g. ModelSim are restricted to old #( ) parameter style instead of newer defparam syntax.
 

ads_ee

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Some tools, e.g. ModelSim are restricted to old #( ) parameter style instead of newer defparam syntax.

You have that backwards....

defparam was defined in Verilog-95 they added #( ) syntax in Verilog-2001. You can still use or abuse defparam in Verilog-2001.

I started using #( ) syntax when the Xilinx tools started supporting it (after lots of complaining by me an a lot of other engineers)

-alan
 
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FvM

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You see that I'm not primarly using Verilog, I suppose you are right, thanks for clarifying things.

I wonder however, why ModelSim didn't accept defparam in mixed language projects, so that I needed to change existing code.
 

FvM

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Thanks! In fact defparam is still supported in Modelsim, which is necessary at least as a legacy measure. But for some reason, not in mixed language designs, when instantiating VHDL components in Verilog text.
 

eng.amr2009

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Thanks people, it really works for Xilinx ISE. Still have problems with modelsim !
Is there any workarounds for modelsim mixed language projects ?
I'm still not much experienced in verilog, I used only VHDL for 3 years.

Thanks in advance
 

FvM

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Does your Modelsim license include mixed language simulation?
 

ads_ee

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yes the #() works in modelsim. I've been using this syntax over many modelsim versions: 6.6e (may be an even earlier version, but that's the oldest I have installed) up to 10.1b.

Have you tried a simple test case? Something like a VHDL register with a generic width and instantiate it in a Verilog top level?

-alan
 

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