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You just have to instanciate module header that would be semantically the same as VHDL entity. When the VHDL module is added to project and you want to use it inside Verilog module, you simply imagine that VHDL component is written in Verilog and use it as if it actually is.
Thanks! In fact defparam is still supported in Modelsim, which is necessary at least as a legacy measure. But for some reason, not in mixed language designs, when instantiating VHDL components in Verilog text.
Thanks people, it really works for Xilinx ISE. Still have problems with modelsim !
Is there any workarounds for modelsim mixed language projects ?
I'm still not much experienced in verilog, I used only VHDL for 3 years.