How to instantiate a RAM verilog model in the synthesizer?

[lordsathish]

Hi every one... I'm new to this domain... i'm working on a design that uses large RAM's... that is the depth of the RAM is only 64byte... but i've to use many such RAM's in parellel... could any one give me idea of the a verilog model of the RAM... and how to instantiate it in the synthesiser...
Thanks in Advance...

 

[kishore2k4]

Re: RAM verilog model

If you are using dual-port RAMs then just write the verilog code for the same and instantiate it like any other module.

 

[verma.ind]

Re: RAM verilog model

You can check the site www.asic-world.com.....
You can get RAM verilog examples in this site.....

 

[shiv_emf]

RAM verilog model

synthesiser ? wht does it mean !
In verilog memory is implemented usings arrays n ram ips r available ...ready made

 

[lordsathish]

Re: RAM verilog model

i'm mean when i synthesis the code... i'm using RTL compiler...

Added after 5 minutes:

hey i'm using a dual port 64byte asynchronous ram... please can any one tell me how to write a verilog model...

Added after 4 hours 30 minutes:

what is the minimum size of RAM in ASIC... can there be a RAM as small as 64bytes...

 

[sridhara]

Re: RAM verilog model

Hi... does anyone know about the memory compiler from cadence... Is it RT SUN...
can any one of you help me to learn using it...

 

[FLEXcertifydll]

RAM verilog model

Not there is no memory compiler from cadence,

Actually almost is from library vendor.

U can try Artisen

 

[littlefield]

RAM verilog model

is the ram come from the vendor?
the vendor should provide you the module

 

[carna]

RAM verilog model

Is there anything special when you simulating the SRAM?