How to insert spare cells ?

[zeese]

insert_spare_cells

I have two questions regarding above.

1) Can I insert spare cells using Synopsys design compiler?

2) What are things that need to be considered if I want to do
compilation for design that have spare cells. What I mean
is do I have to do set dont touch for the spare cells, or make
sure it is connected to hi/low, etc. Please let me know things
that I have to write in my script before compile.

I appreciate your help

 

[silencer3]

dc_shell spare

can u tell why do u want to insert spare cells?. If u are thinking of spare cells from FAB point of view, that will be done in back-end.

 

[zeese]

Actually, I was asked by layout person to do this.

This is the first time I heard about spare cells. So, I'm
still learning. And so far, I only use DC, not physical compiler.

I check the manual, the command does exist in physical compiler,
which is psyn_shell-t> insert_spare_cells -lib_cell .....

So, maybe, it can be done both at front end and backend. In my
case, I was asked to do it, which is need to be done at front end.

So, I need answers for the questions that I posted in my first post.

 

[jjww110]

please read spare cell in dc,let back-end to layout

 

[zeese]

what do you mean by read spare cell in DC?

The only command that I know is "insert_spare_cells",
but that command is not recognized by dc, eventhough
that command is shown if I type dc_shell-t>man insert_spare_cells.

What other command should I use in DC, or does it not working
in DC (back to my question no. 1 in my first post).

 

[RTL2GDSII]

You can create a spare gate module and instantiate it in other modules in upper level.
But you need to tie at least one signal to this spare gate I/O port.
Remember set_dont_touch to this module in DC.

 

[visualart]

you may insert themwhen you layout your chip.
after the place the cell, You may insert the spare cell as same as the insert the filler.

 

[Thinkie]

We talking about spare gates to be used in an possible ECO, right ?

Just make an HDL file with all the gates you want and tell Synopsys
don't touch.

You P&R program will not remove them, just tell it to place them
evenly in your ASIC as you never know where you will need them.

There is a small power penalty that you pay... but generally speaking you
can put a lot of these.

 

[mefirst1808]

How to place spare cells evenly in Soc Encounter???

 

[jbeniston]

How to place spare cells evenly in Soc Encounter???

Look at the commands: createSpareModule and placeSpareModule

 

[kumar_eee]

We use "specifySpareGate" command to place Space cells in SOC Encounter.

 

[rca]

For me they are two king of spare cell:

the spare cell added to the netlist in SOC encounter flow, at the place step, used to fixed some logic bug.

Some spare cell include at the RTL code, to add function requires to fix behavior, more related to analog stuff, example added unused mapped register to directly connected to analog element or reading back some analog info, for fixing/feature fix.