How to insert delay in digital signal?

[tasctasc]

I am designing a circuit in a 90nm CMOS process and I need the ability to vary the delay of a digital signal. The tapeout is in a few days and I'm also very pad limited so I was wondering if there is a way to do this off-chip? Do signal generators typically allow a delay to be inserted in signals?
Any help would be sincerely appreciated.
Kind regards,
Tas

 

[FvM]

Frequency, intended delay?

 

[tasctasc]

Hi FvM,

Sorry for omitting that information. Frequency is ~100 MHz and delay steps are at least 100 ps, preferably 50ps.

Thanks.

 

[edwinc]

You can achieve a delay by using a buffer, where delay is controlled by a grounded capacitor implemented between stages. On the other hand, you can use more capacitance in order to increase delay. It could be on or off chip, but remember than you have more control if it is integrated.

 

[ADITYAVARDHAN]

you can also use D-flip flops to get delay