how to insert delay buffer?

[tavidu]

insert buffers to provide delay

I want to insert several buffer in order to delay a signal, about 2ns at least, but 3ns at most.
After I insert buffers, and do STA, the delay at best case is 2.01ns, but reach 4ns at worst case , more than 3ns :-(
So anyone can help me how to insert delay, that can meet timing at both best case and worst case.
I dont know whether some special library cell can meet these situation.(I use Artisan library)

 

[kshitij_s81]

Can U help me how to insert buffers into DC and then do STA with PT
Waiting for your reply
Kshitij Sukhwal

 

[seanwu]

I always do placement and trial route before inserting clock tree.

 

[ceyjey]

Hi,
You can insert buffers in PrimeTime directly.
Generally speaking, a single buffer does not have that huge timing difference between best case and worst case. You must cascade a series of buffers, right? However, when cascading buffers, it's not a good idea to connect buffers with the same drive strength, say, all the buffers are in 12X. The reason is the input signal may not have enough strength to drive the initial stage cause the input capacitance of 12X buffer is relatively high. The better choice is to increase the buffer size progressively and tune the total delay into the desired zone.
Hope this helps

ceyjey

 

[Kulprashant]

hi,
you can insert the buffer directly in primetime.

with regards,
kul

 

[wkong_zhu]

the exact delay is troublesome in design. Only the exact delay after P&R is reliable. Just run hspice, to try, and fix the delay chain first when you do place and route. then extract the RC, use primetime to analyse it.

 

[wangxu]

Manul inserting buffer is not a GOOD WAY TO SOLVE THE PROBLEM.
TRUST YOUR P&R TOOLS. THEY WILL HELP YOU TO PASS THROUGH THE
STA.

 

[soccer]

if you can not solve this problem in primetime, you can ignore it temporary, and solve it in layout tools by physical method.

 

[jjww110]

please re-synthesis ,let dc do it

 

[power-twq]

that's difficult to realize your dream, because gate's delay can vary 2 times from

best case to worst case, I think you should find other measure to deal with

your problem, there should be another method to conquer with the problem that

you face. good luck.

I want to insert several buffer in order to delay a signal, about 2ns at least, but 3ns at most.
After I insert buffers, and do STA, the delay at best case is 2.01ns, but reach 4ns at worst case , more than 3ns :-(
So anyone can help me how to insert delay, that can meet timing at both best case and worst case.
I dont know whether some special library cell can meet these situation.(I use Artisan library)