How to insert a hierarchy in RTL design

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woshicloud

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can any tool do following operation on RTL code?

from:
module A();
A1 A1();
A2 A2();
endmodule

tomerge A1 A2 into a new module A12)
module A();
A12 A12();
endmodule

module A12();
A1 A1();
A2 A2();
endmodule

Thanks
 

my target is to insert a hierarchy into an RTL design, not netlist. Can dc_shell do such operation?
 

Hi, have you looked into VerilogMode EMACS? While not perfect, it could probably automate some of the tasks.
 

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