How to initialize registers to zero on reset?

[rsrinivas]

hi all
i have built a register file which has to initialize to zero on reset.
say an array of 16 registers which are 64 bits wide each.
howdo i initialize them on reset.

module regfil1(clk,rst,addrread,addrwrite,din, writep, readp, dout);
input clk;
input rst;
input [63:0] din;
input readp;
input writep;
input [4:0] addrread;
input [4:0] addrwrite;
output [63:0] dout;

parameter MAX_COUNT = 5'b01111; // topmost address in register file.

reg signed [63:0] dout;

always @(posedge clk) //problem here works only on posedge clk
begin : rst_blk
integer i;
if(rst)
for(i=0;i<=MAX_COUNT;i = i+1)
begin
regbank <= 64'h0000000000000000;
end
else if (writep == 1'b1) begin
regbank[addrwrite] <= din;
end
end

always @(posedge clk)
begin
if(readp == 1'b1 && !rst) begin
dout <= regbank[addrread];
end
end

endmodule


it works only on posedge clk, does the for loop work on each posedge clk or is concurrent i.e at a posedge clk the whole of for loop is executed
any alterations or suggestions pls

 

[nand_gates]

Re: all zero on reset

The for loop will get executed in one posedge clk when rst is high.

 

[rsrinivas]

all zero on reset

so on one posedge clk if reset is high the whole reg bank will be zero??

 

[aji_vlsi]

Re: all zero on reset

so on one posedge clk if reset is high the whole reg bank will be zero??

Yes, that's how this code is written and hence yes. Did you simulate your code? What did you see? Did you see any behavior different than expected?

Regards
Ajeetha, CVC
www.noveldv.com

 

[rsrinivas]

all zero on reset

i have simulated in NCsim but the simulator shows no value assigned on reset.
i am a bit confused.

 

[echo47]

all zero on reset

Your code doesn't define regbank. You need something like this:
reg [63:0] regbank [0:MAX_COUNT];

If you are targeting a Xilinx FPGA (maybe others too), beware that your single-cycle reset will force the synthesizer to implement regbank as 1024 flip-flops and lots of multiplexers.

 

[rsrinivas]

all zero on reset

Hi echo
thanks for the correction.
I have it in my code i forgot to paste it ere.
u say tat a lot of resources will be consumed right.
(64*16 = 1024 FF's).
i have a spartan 3e.
other than resource usage wat problems may occur.

cheers
srinivas

 

[aji_vlsi]

Re: all zero on reset

i have simulated in NCsim but the simulator shows no value assigned on reset.
i am a bit confused.

Try adding $display/$monitor. My guess is since it is a memory, the values are not dumped by default in NCSIM. How do you dump the values - using $dumpvars? TCL? I vaguely remember there is some thing special that needs to be done to display memories, I can find it out later and tell you. Meanwhile try adding $display and tell us how you dump

Good luck
Ajeetha, CVC
www.noveldv.com

 

[echo47]

all zero on reset

I just noticed that your address buses have 5 bits but your MAX_COUNT is only 15. That seems strange, but maybe you did it deliberately, although you originally said only 16 registers. Five bits means 32 registers, and 2048 flip-flops. In that case, the regbank definition should be:
reg [63:0] regbank [0:31];

I suppose there's no problem with consuming lots of registers and multiplexers, if you have plenty of space in your FPGA, and if you don't mind reduced speed due to high fan-out and long routes.

I routed it into a Spartan-3E, and a quick-and-dirty post-route simulation looks ok.

 

[rsrinivas]

all zero on reset

Hi
thanks 4 thereply.
the code i posted ere is just a rough one i wrote.
the reg bank is wat i am lookin is in for a design which holds temporary values.
i have the option of having a dualport ram also.
which one is better any sugesstions.