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How to increase the length of each scan chain in DFT?

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newcpu

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DFT help

Hi,
I am confused by a dft problem now. Since the scan chains from fontend are not enough, the test coverage is a little low. Someone told me that increasing the length of every scan chain could resolve this problem. But I did not constrain the the length of every scan chain. The test coverage is still not high. What should I do to increase the length of each scan chain and the test coverage?

Best Regards,
newcpu
 

hawk_chenbo

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DFT help

The length of each scan chain is determined by your design itself not constraints. You should check your test for testability. If your design is good at testability, you need to check the ".spf" file generated by DFT compiler.
 

Garbielhijo

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Re: DFT help

The constraints of length of a chain is not a prioritity constraint. If you have low coverage check for Testability issues for example:
Not reset controlability.
Clock gatting
Clock domains
Latches
If you avoid this problems your coverage will increase.

All this problems must be reported in the Log files. If yoiu look for more infor chec www.synopsys.com, there they have some documents about DFT
 

newcpu

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DFT help

Thanks a lot for your help. What is the ".spf" file generated by DFT compiler? How to generate it?
And about the latches, do you mean the lookup latch?
 

free1983

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DFT help

When you finish inserting scan at the top level, write the Standard Test Interface Language (STIL) test protocol file for TetraMAX using the write_test_protocol command. You should also write out a Verilog or VHDL top-level netlist for use in TetraMAX.
dc_shell> write_test_protocol -format stil -out top.spf
dc_shell> write -format verilog -output top.v
 

jcchan

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Re: DFT help

You must to check dft violation first.
 

xworld2008

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DFT help

You should list some statement , where you coverage is low, if not you can't get a clearly answer. And dft coverage low , major at serval sit. such as latch , internal generate clock, internal reset or set, clock domain, some macro : ram,rom. and some macro you should wrap it.
 

newcpu

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DFT help

Thanks a lot.
The scan chain Error is: Chain c16 blocked at DLAT gate top_core0.dsp_top.audio_top0.aud_zspsubsys.LOCKUP (863572) after tracing 107 cells. (S1-1)

Best Regards,
newcpu
 

deodar_li

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Re: DFT help

From your error message, you can set transparent attribute on these latches.
 

appleleafs

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DFT help

The length of the scan chain would NOT have much to do with the test coverage.
The DFT violations reported by the tools should be checked carefully instead, and fixed.
 

Elias.xie

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DFT help

Another facets that can low your test coverage are:
1. generated clock logic
2. generated reset logic
You should bypass them by test mode signal
 

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