How to increase speed of preamp

[Ravinder487]

Hi all,
I've designed preamp with CMFB(schematic attached).Its taking 20nS to get settle.I need to insert this preamp in a ADC working at 500MSPS.unity gain BW of preamp is 835MHz and gain is around 26V/V.Preamp is biased at 45uA.
Does the settling of this preamp is limited by BW or slewrate?How can I increase its speed?
In general, what(settling time or bandwidth) will limit settling time of any amplifier?Is there any rule of thumb relating these parameters?

 

[Braski]

bandwidth and slew rate are generally related. the settling is generally limited by slew rate in the first part of the transient, then by bandwidth. to increase speed, you should increase unity gain BW. to make this, generally you have to increase the current consumption.

 

[lamoun]

What is the -3db frequency? Assuming a single pole response it should be around 45Mhz => RC = 3.5ns that is 5~6RC = ~20ns which sounds about right. Increasing GBW, as Braski said, will decrease the settling time.

Bear in mind that a preamp with f3db = 50Mhz is really bad for the linearity of a 500MSPS ADC. If you don't have a S&H you should strive for f3db~5*F_Nyquist
What kind of ADC do you design? Have you specifications about SFDR?

 

[Ravinder487]

Thanks lamoun.
3dB-frequency is 66.7MHz and settling time of around 11.56nS.I'm designing SAR ADC with charge redistribution DAC.
5*nyquistrate comes to be around 2.5Ghz(=5*500MSPS).Is it possible to achieve this!!??
If I increase slewrate then I need to increase the size of all so as to keep them in saturation which inturn increases capacitance at the output node.Hence my slewrate and bandwidth will decrease.
Same problem I've faced in design of high GBW OTA.

---------- Post added at 10:41 ---------- Previous post was at 10:35 ----------

please go through my last post in this thread https://www.edaboard.com/threads/205209/

 

[lamoun]

Well depends what you need the ADC for.
For communications you need good dynamic characteristics all around the signal bandwidth. (SNR / SFDR / Intermodulation)
"R. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edition, Kluwer, Boston, MA, 2003." (in a chapter called "limitations of comparators" or something)

I haven't studied SAR ADCs so don't know if this applies to you, but since the architecture uses a S&H circuit everything after the S&H has relaxed specifications.

As for the 5*Fnyquist, I mean 5*250Mhz -> 1.25Ghz still high enough. You can easily achieve this, by cascading low gain diff-pairs (R load) but this is done on high speed flash ADCs.
(And to clarify even further you probably care for 5*signalBW which might be even lower depending your specs)