how to increase sampling rate in FPGA

[arash rezaee]

hello every one
I am using xilinx 3s1600e FPGA and my ADC data is sampled at 96KHz. But in my progress I need to increase my sampling rate inside the FPGA.
How can I increase it?

Thanks
Arash

 

[lucbra]

the easiest way is to double the frequency (to 192kHz)
copy your samples to the new register

 

[arash rezaee]

will you please explain more? Actually I want to increase it into 2MHz.

Regards

 

[lucbra]

then it will be better to fill a FIFO with the samples.
assuming you want to increase until 1.536MHz, then you will need to make 16 copies of your original sample (1.536MHz / 96kHz = 16). With 21 copies, you'll get aprox 2MHz.

In second thought, you might use a clock enable to resample the incoming data too.

something like:

process(clk, rst)
begin
   if rst = '1' then
      data_out <= (others => '1')
   elsif rising_edge (clk) then
      if clken = '1' then
         resampled_data_at_whatever_frequency <= sampled_data_at_96khz;
      end if;
   end if;
end process

the clken signal is then at the desired frequency, in your case 2MHz.

 

[arash rezaee]

Dear lucbra
Thanks for your all help.
But
It didn`t work. Let me explain more about my project. I have 5KHz sinusoidal signal which I pass it through ADC and after that I pass it through LPF in FPGA.Then I want to add some value to it. after I add some value to the signal, It works well and I have 5KHz signal clearly but I have 96-5 and 96+5 in my spectrum too. How can I increase the sample rate of incoming signal from ADC with out changing the setting of ADC. I mean inside the FPGA.

Regards

 

[permute]

what exactly are you trying to do?
1.) increase the sampling rate of the ADC in order to sample higher frequencies (or more bandwidth).
2.) interpolate between sampled data in order to provide data to a system that expects a higher sample rate. In this case, there is still only 48khz of bandwidth.
3.) retransmit samples for some reason. This is the 0th-order interpolation from #2. It differs in that #2 generates fairly smooth curves, while #3 does not.

The first would require running the ADC interface at a faster rate, and is application specific. more information on the ADC would be required, as well as information about the analog filtering before the ADC.
The second requires some form of interpolation. polyphase filtering is fairly easy and has efficient implementations. Other methods also exist depending on the exact requirements.
The third is shown in lucbra's posts. I'm not sure why you would do this.

 

[lucbra]

permute, thanks for the post.
It appears to me that OP has problems with nyquist, but I'm not sure about it.

I first thought is was indeed running the ADC at a higher sampling rate, but as he mentioned 'inside the FPGA', I assumed a resampling (or retransmission as you call it).

A block diagram or a better explanation would help

 

[permute]

Dear lucbra
Thanks for your all help.
But
It didn`t work. Let me explain more about my project. I have 5KHz sinusoidal signal which I pass it through ADC and after that I pass it through LPF in FPGA.Then I want to add some value to it. after I add some value to the signal, It works well and I have 5KHz signal clearly but I have 96-5 and 96+5 in my spectrum too. How can I increase the sample rate of incoming signal from ADC with out changing the setting of ADC. I mean inside the FPGA.

Regards

you have a sampling rate of 96ksps. how are you determining the spectrum? 91kHz would be the first alias of 5khz. If you are doing an FFT, the only way to remove it would be to use complex data. this is because there isn't a way to uniquely determine 5khz from 91khz (or 101khz or several others). The other solution would be to simply ignore frequencies > 48khz as these would all be aliased.

if you switch to a 2MSPS sampling rate, you would have 5kHz and 1995kHz.

 

[FvM]

The question isn't clear. Are you talking about sample rate conversion of existing samples (interpolation filter) or increasing the ADC sample rate? In the latter case, you have to ask for the ADC hardware specification in a first place.

P.S.: I didn't yet notice post #5. According to it, it's a rate conversion problem. The first suggestion of simply repeating samples won't remove the image frequencies completely. For optimal performance, you need an interpolation filter. A CIC interpolator is the most simple method to do it.

 

[arash rezaee]

The question isn't clear. Are you talking about sample rate conversion of existing samples (interpolation filter) or increasing the ADC sample rate? In the latter case, you have to ask for the ADC hardware specification in a first place.

P.S.: I didn't yet notice post #5. According to it, it's a rate conversion problem. The first suggestion of simply repeating samples won't remove the image frequencies completely. For optimal performance, you need an interpolation filter. A CIC interpolator is the most simple method to do it.

Would you please tell me more about CIC interpolator ? Besides, inside FPGA I passed the signal through Low pass filter and it remove frequencies more than 15KHz. I use FIR filter which I created first with matlab and then pass the VHDL into FPGA. so How can I work with CIC filter? I have to remove frequencies more than 15KHz. CIC filter can be implement after LPF or it can remove frequencies more than 15KHz and also up sample the sampling rate?
regards

 

[FvM]

CIC is used in two variants, for rate downconversion (averaging filter) and upconversion (interpolating filter). As a brief introduction, see Cascaded integrator-comb filter - Wikipedia, the free encyclopedia. Unfortunately the interpolating variant is only mentioned in a side remark referring to literature.

A verbose discussion can be found in Uwe Meyer-Baese "Digital signal processing with Field Programmable Gate Arrays". There are also many internet sources related to CIC filters.

At least Altera and Xilinx have CIC IP cores.

 

[arash rezaee]

thanks for all your replies

To FvM

I used CIC filter from xilinx core ( I use xilinx 3s1600E). some times when I have noise or amplitude of input changes so fast, the result of CIC is unstable and I have triangular and other shapes in my output. I up sampled my with 32 times and I used 6 stage for this CIC core. what can I do for this problem? Is it the properties of CIC filter or I have some thing wrong?

Regards

 

[FvM]

A higher order CIC has a smooth frequency characteristic, there shouldn't be "triangular" waveforms. By design, there's no risk of dynamical or statical input overload as far as I'm aware of.

An interpolating CIC however relies on a correct reset and no timing violations of clock and input signals, otherwise the integrators can run wild. In contrast to a downsampling CIC, it can't recover on it's own.

I don't use the Xilinx CIC core, but I simply presume that it's state of the art.