How to increase Maximum Available Clock Frequency in IP Core

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TuAtAu

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Hi all,

I am designing a IP CORE/Soft Microprocessor, ARM based, RISC, 5 stage PIPELINE, CACHE, DSP, ALU, HAZARD CONTROLLER etc.

Currently using Xilinx xc3s1200, after Implementation, it say maximum available frequency is only 20MHz.

I wish it to reach 100MHz!

What is the problem? What actually limit the clock?
any idea?
 

Have a look at the timing report - it will identify your longest paths. If you're new to timing closure, consider reading the Xilinx Timing Closure User Guide.
 
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    TuAtAu

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Thanks joelby, I will study about it
 

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