how to include vhdl in verilog?

[godis_knugen]

verilog include

is there an easy way to put a design in vhdl inside a verilog design?

i have a nice dynamic verilog file with port declarations towards the external hw, but i want to write my own logic in vhdl. not so familiar with verilog yet.

can i write some kind of wrapper for the vhdl? if so, how?

 

[echo47]

verilog include vhdl

Which HDL compiler software are you using?

With ModelSim and Xilinx XST, I can build projects that include both Verilog and VHDL source files without doing anything special. VHDL can instantiate a Verilog module, and vice-versa, without using any wrapper file. But don't mix Verilog and VHDL source code in the same file, use separate files.

 

[godis_knugen]

include vhdl

im using xilinx ise 9.1

have tried using the verilog file as top and simlpy instantiate the vhdl as a module,
example:
u_l user_l(
. clk(usr_clk),
.addr(ht_wr_addr)
);

but it says unexpected error when i run synthesis.

 

[echo47]

ise include path

Mixed-language compiling usually works in ISE XST. You may have triggered some other bug that caused the "unexpected error" crash. Maybe an ISE update would help you.

Try this example. It works fine in ISE 9.2.04:

module top (clk, icount);
  input         clk;
  wire    [3:0] q;
  output  [3:0] icount;

  count4 counter(.clk(clk), .Q(q));

  assign icount = ~q;
endmodule

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count4 is
  port
  (
    CLK : in  std_logic;
    Q   : out std_logic_vector(3 downto 0)
  );
end count4;

architecture archi of count4 is
  signal tmp: std_logic_vector(3 downto 0) := "0000";
begin
  process (CLK)
  begin
    if (rising_edge(CLK)) then
      tmp <= tmp + 1;
    end if;
  end process;
  Q <= tmp;
end archi;

 

[godis_knugen]

rpsyscore_api.v

ok, that worked, but not when i have this:

module top `include "rpsyscore_api.v"

wire clk;
wire [3:0] q;
wire [3:0] icount;

count4 counter(.clk(clk), .Q(q));

assign icount = ~q;
endmodule

where rpsyscore_api.v specifies the ports and the "verilog include path" under synthesis properties is set to the destination of the api file.

then i get :
error Analyzing hierarchy for module <top> in library <work>.
ERROR:Xst:2683 - Unexpected error found while building hierarchy.

 

[echo47]

include vhdl to verilog

That worked for me in both ISE and ModelSim. I assume rpsyscore_api.v contains this line:
(clk, icount);

I run ISE from command-line scripts, not from Project Navigator. The fragment line in rpsyscore_api.v looks like gibberish, not a Verilog module, so try giving it a different extension than ".v", or put it outside the Verilog search path, so Project Navigator doesn't try to automatically interpret it as a Verilog file. That's just a guess.

 

[godis_knugen]

instantiate vhdl block in verilog

The fragment line in rpsyscore_api.v looks like gibberish, not a Verilog module, so try giving it a different extension than ".v", or put it outside the Verilog search path, so Project Navigator doesn't try to automatically interpret it as a Verilog file. That's just a guess.

but rpsyscore_api.v is a verilog module ...
looks something like:

(
usr_clk,
usr_rst,
clk,
icount,
...

);

////////////////////////
// Port Declarations
/////////////////////////

input usr_clk;
input usr_rst;
....

/////////////////////////////////
// Configuration-Specific Output Port Settings
///////////////////////////////

"here goes lots of `ifdef and `ifndef statements"


------------------------------------------------------------------------------------
i simply placed the .vhd file in the project directory. here named count4.vhd

 

[echo47]

ise design verilog vhdl

rpsyscore_api.v may be fine when "included" into your top file, but by itself it is incomplete. It begins with a parenthesis instead of a 'module' keyword.

In other words, you put a non-Verilog file into ISE's include path and gave it a ".v" extension, so ISE may be stumbling over it.

 

[godis_knugen]

can we mix vhdl and verilog in xst

aha, i see. oh and bythe way the property i set was "verilog include directories" under synthesis- properties.

Nope, didn´t help.

but it works if i comment the line " count4 counter(.CLK(clk), .Q(q)); " that instantiates the vhdl block

 

[echo47]

`include verilog vhdl

I can't reproduce your problem. Can you upload your various source files to be sure we are both looking at the same files?

 

[godis_knugen]

how to write a verilog wraper for vhdl design

finally it works, i tried starting a new fresh project and using ise9.2 with the latest sp. i still dont know why it didn´t work before though. ¨
anyway, thanks for the help.

 

[echo47]

ise verilog `ifndef

That's good news! Maybe your code was simply triggering some obscure bug in the older version.

 

[ishwarayya]

Dear echo47 & godis_knugen ,

i have tried the counter example in modelsim XE3/starter 6.3c version,by modifiying the code as like below

*********top.v file*******************
`include "count4.vhd"
module top (clk, icount);
input clk;
wire [3] q;
output [3] icount;

count4 counter(.clk(clk), .Q(q));

assign icount = ~q;
endmodule

*******************************


*********count4.vhd file****************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count4 is
port
(
CLK : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end count4;

architecture archi of count4 is
signal tmp: std_logic_vector(3 downto 0) := "0000";
begin
process (CLK)
begin
if (rising_edge(CLK)) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
************************

---> but when i simulate .v file its shows following error

** Error: count4.vhd(1): near ";": syntax error, unexpected ';', expecting "STRING_LITERAL"

is there any extra settings u did while simulating ..?

regards,

ishwar

Added after 23 minutes:

Dear echo47 & godis_knugen ,

i have tried the counter example in modelsim XE3/starter 6.3c version,by modifiying the code as like below

*********top.v file*******************
`include "count4.vhd"
module top (clk, icount);
input clk;
wire [3:0] q;
output [3:0] icount;

count4 counter(.clk(clk), .Q(q));

assign icount = ~q;
endmodule

*******************************


*********count4.vhd file****************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count4 is
port
(
CLK : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end count4;

architecture archi of count4 is
signal tmp: std_logic_vector(3 downto 0) := "0000";
begin
process (CLK)
begin
if (rising_edge(CLK)) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
************************

---> but when i simulate .v file its shows following error

** Error: count4.vhd(1): near ";": syntax error, unexpected ';', expecting "STRING_LITERAL"

is there any extra settings u did while simulating ..?

regards,

ishwar

 

[FvM]

You can't include VHDL code in a Verilog file. Both files have to be compiled separately.