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how to improve the match of folded cascode amplifier

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Junior Member level 3
Aug 20, 2009
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i am designing a folded cascode amplifier,with high gain and low current required,when i ever i run a monte carlo simulation in cadence while only mismatch is selected,the DM gain and CM gain vary a lot,means mismatch is really bad,can anybody tell me how to improve the mismatch of the whole circuit???thanks

increase L or area of the input transistor pairs.

The current mirror portion includes a non-trivial amount of gain as well. Interdigitate the mirrors, increase channel lengths.

I am also facing similar problem. Mis-match is screwing my open loop gain. For e.g. i ran MC for 30 iterations (suggested by UMC MC datasheet) and my open loop gain which was designed for around 7K drops to few 1K. Only one or two iterations hits my open-loop gain.

I will highly appreciate any suggestions on this problem.


Hello chichi,

What setup do you use for DM and CM gain simulation?
Have you set the amplifier's inputs with two independent voltage sources as many newbies do?
Or used unit gain buffer configuration with corresponding circuit for AC sim?
In the first case you can easily get DM and CM gain variation for mismatch simulations.

Meanwhile, you have to rely on offset to judge how good is mismatch.
In common sense you can improve matching by having large device sizes, high transconductance efficiency (Gm/Id) for differential pair and cascode devices,
low (Gm/Id) for current mirrors. Normally only the diff. pair and 2 mirrors impacts on offset of folded cascode amp.

I've personally never simulated DM gain during mismatch analysis since it doesn't make a sense.
If setup/circuit is correct no big variation of DM gain is expected due to mismatch.
From other side DM gain is normally checked during PVT simulation and it can/should vary a lot.


Hi Denis,

I have done the offset calculation of my folded cascode OTA.

In my test bench OTA is configured as unity gain buffer. Then using wavescan I measure the difference between input and output during monte-carlo simulation with Mis-Match & process variation. The resultant file is imported to matlab to measure the 3-sigma offset.

Can you please verify if this approach is proper? Or am I missing something here?


Hello Nandish,

Yes, offset is a difference between inputs for unit gain config (you deal with single ended OTAs regarding to response).
The way how you extract sigma values depends from tools you have.
In general if you have enough computer resources/tools' capability/time you can estimate offset for different temperatures, supply voltages, on the edges of input CM range (ICMR), etc.

An other point could be a matching between ICMR and output range. If your inputs signals are in ICMR but outside of output range you and vice versa will not get desired amplification (huge offset).
You can make setup more flexible regarding output level if include a little circuit (2 vcvs and 1 vdc) in negative feedback. Sorry, can't illustrate how.
If you need you can try to follow to text description:
1st vcvs (InPos to output of OTA, InNeg to vdc, OutPos to 2nd vcvs, OutNeg to gnd), vdc sets desired output voltage of OTA, 2nd vcvs (InPos to 1sr vcvs, InNeg to gnd, OutPos to negative input of OTA, OutNeg to positive input of OTA), now loop is closed.
All vcvs'es use gain = 1, and you also have vdc setting input CM level which is connected to positive input of OTA. Between 2 vcvs you can include RC or LC LPF circuit for AC simulations or probe for STAB analysis.
In series with negative input you can include AC source for AC sims.

Hi Dennis,

Thanks a lot !!! This is very useful information that you have shared with me. Many thanks for it. Following your instruction i have created a quick schematic of test bench. Though might be useful to other community fellas. Can you please cross verify whether its correct or not.

Also Dennis, how about biasing the input pairs if the output common mode and input common mode are different. How to make sure that during this simulation the input pairs remain in saturation.

Thanks again for your informative post.



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Seems I did not write it clearly "you also have vdc setting input CM level which is connected to positive input of OTA".
In circuit you drawn you have to add VDC source and connect it to positive input of OTA.
This VDC will set input CM level. An AC source in series with the VDC can be used for CMRR sim
(but only one Ac source should be enabled at the same time).

Now you have two VDCs, one for input CM and other one for output level.

Location "insert iprobe here" corresponds to place where you can break circuit for AC or STAB simulation while circuit is balanced at it's DC operational point.
For Cadence's STAB analysis you can insert VDC=0V in series with break point (and point out it in analysis setting window),
or you can use conventional technique of AC analysis with LPF (RC or LC) inserted.
Or ever you can use "sp1tswitch","sp2tswitch" elements form analogLib for which you can set position depending from analysis you do (lock loop for DC and break it for AC).
For DC: OutPos of VCVS1 == InPos of VCVS2
For AC: OutPos of VCVS1 == floating, InPos of VCVS2 == GND
Hi Denis,

Thanks for your response. It is very helpful.

Even before I can measure offset of my folded cascode OTA, I am facing error while measuring the open loop gain of the OTA.

I do the following in my MC simulations:

1) Provide input Vcm to the OTA and leave OTA in the open loop.
2) Set .ac from 1Hz to 10GHz
3) Set the sigma to 3
4) Run MC with process and mismatch for 200 iterations.
5) Matlab post processing for counting number of times OTA meet the open loop gain requirement.

I want an open loop gain of 5000 and from 200 runs hardly 5-10 iterations meet my spec.
Is there any closed loop technique to estimate open loop gain?

Otherwise can you please point out what am I doing wrong in current simulation setup? Please kindly bear with me as I am new to analog circuit design.

Thanks a lot for both of your older post. Please suggest something on the above mentioned problem.

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You have to know that AC analysis starts from DC operation point computation (or simply from DC analysis).
After that circuit is linearized around operational point and AC analysis is carried out.
If your OTA is imbalanced by some offset (e.g. due to MC sims) it will impact on gain.
Just imagine what should be on output if multiply expected offset by expected gain?:)

So you have to balance OTA for computing a real gain. This means that for DC analysis your OTA should
have stabilizing by negative feedback around, or closed loop, or e.g. to be in unit gain configuration as frequently used.
For AC analysis (after DC) loop should be open (aka broken), otherwise gain will be determined by negative feedback.
To break loop for AC analysis (not for DC) RC/LC LPFs are used as well as other components I described before.

Try to start with offset MC simulation (conventional DC) than if you succeed you can proceed with gain simulation (DC+AC).
Personally I use MC for offset prediction, and I never use MC sim for gain, I use PVT instead.
This is because MC mismatch has a negligible impact on gain while MC process just underestimates impact of process on gain.

you should design your circuit's bias circuit smart, if some value is changed on the main circuit, the bias circuit should follows it. of course, some mismatch problems cannot be fixed.

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