How to improve S21 in LNA design??

[cqmyg5]

I am learning to design a typical simple LNA made of two cascade MOSes on 0.18um process. but it seems defficult to improve the S21 from 10dB(current) to 16dB(target).

The Ld is 12nH, 25ohm now. I could't increase this inductor of drain and because of area limit and the area of MOS is a little big now (w/l=700u/0.18u).

So, what is the other way to reach the S21=16dB?

 

[flatulent]

some ideas

I am not an expert in RFIC design. Since no one else has responded, let me give some generalized suggestions that may inspire you to have a flash of insight on what the right thing is to do.

1. Can you add some parallel capacitance to the inductor so that at your operating frequency the total impedance is larger?

2. Can you use a circuit topology where the impedance of the next stage or load is smaller so that the inductor in parallel does not reduce the total load impedance as much?

 

[BigBoss]

W/L ratio is incredibely high. Gate-Substrate capacitance decreases the S21 anormally.

Please check your circuit and calculate minimum W/L ratio that you need.

Which frequency you work at? If you work 500MHz and over , 12nH Source indcutance is huge..

There are some mistakes in your circuit I believe. If you don't mind , please post it to investigate..

 

[cqmyg5]

the Width of the MOS is calculated by w=1/(3*w*l*c*rs) to minimize the NF; and the Ld is not a source inductor but a drain (load) inductor. the operating frequency is 2.5GHz.

 

[victoriya]

i think you had a mistake in calculatingg the wopt of your device .
for 2.5gighz i think the 4or 5nh of load inductor with a few femto hundereds of load capacitance will be enough to get such s21.

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