How to improve reference buffer transient load regulation?

[alias0823]

how to improve load regulation

Hi all

When I design a buffer for voltage reference
There is a spec called transient load regulation
Its test circuit is as picture

Vin="Vsupply/2"; and Vtl transient from "Vsupply" to "0" and "0" to "Vsupply" within 0.1usec. Then I can monitor the voltage of Buffer output with a voltage peak.

My buffer design is a two stage amplifier, and I try two compensation method.
One is pole split method with miller compensation, and another is cascode miller compensation.
My question is how to improve transient load regulation? it means smaller voltage peak at buffer output.

Thanks

Added after 7 minutes:

Sorry, R=1k ohm.

 

[tycheng]

buffer circuit load regulation

Check the control theory......
You need to have a high damping ratio

 

[jcpu]

load regulation improve

Hello,

It is not clear how Vtl is related to the circuit,
and the other end of 1Kohm resistor is open??

Best Regards,

 

[alias0823]

Re: How to improve reference buffer transient load regulatio

Hello,

It is not clear how Vtl is related to the circuit,
and the other end of 1Kohm resistor is open??

Best Regards,

Sorry, If my picture is not clear
Vtl is a voltage source of "0" to "Vsupply" swing, and Vi=0.5*Vsupply. Then It means the buffer need to source or sink current I=(0.5*Vsupply)/R when Vtl change its polarity.

Added after 23 minutes:

Check the control theory......
You need to have a high damping ratio

Sorry, could you translate your system view to circuit level design?
I had monitor its close loop AC response, and no magnitude peak, which mean
the dampling factor is high enough.