How to improve linearity of a MOS or Bipolar Circuits

[libertador]

Hi,
My post-graduate thesis is wideband open loop buffers/amplifiers. Hence, linearity is the most important spec. All of the papers that i found are about linearization techniques like degeneration resistors. Effects of dimensions that MOS widths/lengts, emitter area, resistors values or bias currents, voltages were not mentioned anywhere. So I determined this values only from simulation results.
Do you have any clue that to improve linearity not only with basic linearization techniques but also dimensions? Also do you know any paper or notes about this issue?

Thanks All.

PS: If you want i can add cicuits that i have designed.

 

[uncle_urfi]

Some thoughts...

One technique is to use transistors with different dimensions (hence different Vts) in parallel, such that they turn on at different input voltage levels. This is employed to provide a linear V-I relationship in biasing circuits and V-I converters for VCOs.

Also calibration can be performed using either a bandgap reference, or an input frequency that is derived from a crystal. Individual gains of blocks can be trimmed to reduce non-linearity of the desired output.

Check Baronti et al, "A Technique for Non-linearity Self Calibration of DLLs" IEEE. Trans. Instrumentation and Measurement., August 2003