adscrz
Member level 1
How to improve Fmax ?
I found some combination logic between two registers after compilation with below code, so the Fmax only 100.8MHz,
Could you give me some suggestion?
I want to add some registers , but I do know how to add it
Thanks.
// State Machine - Next State Assignment
always @(posedge sys_clk or negedge reset)
if (!reset)
begin
state <= verital_blank ;
clk_counter <= 16'h0 ;
line_counter <= 9'h0 ;
even_line <= 1'h0 ; even_row <= 1'h0 ;
end
else
begin
clk_counter <= clk_counter + 1 ;
case (state)
verital_blank: begin
//Vertical blanking :38,074 pixel clocks
even_line <= 1'h0 ; even_row <= 1'h0 ;
if ( clk_counter == 16'd38074 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
frame_start_blank: begin
//Frame start blanking, R0x05-23 = 71 pixel clocks
even_line <= 1'h0 ; even_row <= 1'h0 ; //standard output
//even_line <= 1'h1 ; even_row <= 1'h0 ; //for C113 only
if ( clk_counter == 16'd70 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
active_data: begin
//Active data time, R0x04 = 752 pixel clocks
even_row <= ~even_row ;
even_line <= even_line ;
//if ( clk_counter == 16'd751 )
if ( clk_counter == 16'd4 ) //for speed up testing
begin
state <= next_state;
clk_counter <= 16'h0 ;
line_counter <= line_counter + 1 ;
even_line <= ~even_line ;
if ( line_counter == 9'd479 )
begin
line_counter <= 9'h0 ;
end
end
end
horizontal_blank: begin
//Horizontal blanking, R0x05 = 94 pixel clocks
even_line <= even_line ; even_row <= 1'h0 ;
if ( clk_counter == 16'd93 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
frame_end_blank: begin
//Frame end blanking, 23 (fixed) pixel clocks
even_line <= even_line ; even_row <= even_row ;
if ( clk_counter == 16'd22 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
default: begin
clk_counter <= 16'h0 ;
even_line <= even_line ; even_row <= even_row ;
end
endcase
end
I found some combination logic between two registers after compilation with below code, so the Fmax only 100.8MHz,
Could you give me some suggestion?
I want to add some registers , but I do know how to add it
Thanks.
// State Machine - Next State Assignment
always @(posedge sys_clk or negedge reset)
if (!reset)
begin
state <= verital_blank ;
clk_counter <= 16'h0 ;
line_counter <= 9'h0 ;
even_line <= 1'h0 ; even_row <= 1'h0 ;
end
else
begin
clk_counter <= clk_counter + 1 ;
case (state)
verital_blank: begin
//Vertical blanking :38,074 pixel clocks
even_line <= 1'h0 ; even_row <= 1'h0 ;
if ( clk_counter == 16'd38074 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
frame_start_blank: begin
//Frame start blanking, R0x05-23 = 71 pixel clocks
even_line <= 1'h0 ; even_row <= 1'h0 ; //standard output
//even_line <= 1'h1 ; even_row <= 1'h0 ; //for C113 only
if ( clk_counter == 16'd70 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
active_data: begin
//Active data time, R0x04 = 752 pixel clocks
even_row <= ~even_row ;
even_line <= even_line ;
//if ( clk_counter == 16'd751 )
if ( clk_counter == 16'd4 ) //for speed up testing
begin
state <= next_state;
clk_counter <= 16'h0 ;
line_counter <= line_counter + 1 ;
even_line <= ~even_line ;
if ( line_counter == 9'd479 )
begin
line_counter <= 9'h0 ;
end
end
end
horizontal_blank: begin
//Horizontal blanking, R0x05 = 94 pixel clocks
even_line <= even_line ; even_row <= 1'h0 ;
if ( clk_counter == 16'd93 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
frame_end_blank: begin
//Frame end blanking, 23 (fixed) pixel clocks
even_line <= even_line ; even_row <= even_row ;
if ( clk_counter == 16'd22 )
begin
state <= next_state;
clk_counter <= 16'h0 ;
end
end
default: begin
clk_counter <= 16'h0 ;
even_line <= even_line ; even_row <= even_row ;
end
endcase
end