Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
if you want to design some core then you can try using the cordic algorithm...
there references available in the net about this algorithm which uses only shift and add operatios to compute sine as well as cos...
LUT method is faster, you generate the address using the input data, and pick the value from the ROM; but the accuracy depends on the LUT size, or sampling density. Since sin/cos is periodic, you can combine LUT with some taylor interpolations to improve the accuracy.
CORDIC is relatively slow, the accuracy depends on the number of iterations, so higher accuracy means longer latency. But it only requires add/shift, very area efficient.
Please notice, that VHLD AMS or any other HDL that can calculate sine and other mathematical function, don't help somehow to get synthesizable code for a FPGA calculating sine function. They just support this function for simulation or can calculate a ROM table.
I understand, that you want the sine function for float numbers. Known Cordic cores are using fixed point only, e. g. from opencores.org or Xilinx. In contrast, usual FPGA floating point packages have 4 fundamentals and squareroot only.
I think, if full floating point resolution is needed, you should implement an usual numerical math iterative alrorithm. That's also done by processor FPU supporting higher math functions. A lot of literature can be found regarding implementation details.