how to implement the global gated clock in RTL level?

[irun2]

Hi all,
In low power design I've learned that there're some techniques, and one of them is clock gating. There're global/local clock gating.
I know following codes can infer the local one with some proper power compiler directives.
always @(posedge clk)
...
if(clk_en)
q<=d;
...
But in what coding style should be written if I want the global gated clock way?

 

[rca]

I don't know what you mean by global gated clock.
Gated clock in rtl mean to generate a gated clock enable instead gated data enable.

 

[lostinxlation]

When you talk about synthesis, no one can answer your question without telling us which synthesis tool you are referring to. All the synthesis tool has different feature, coding style, etc..

If you use DC, I think XG can do the global clock gating.