How to implement opamp design in ASIC?

[embeddedlover]

I want to implement Opamp in ASIC.
As i am fairly new can anybody please guide me where i have to start.
I want to a non-inverting gain amplifier.

 

[Syswip]

opamp is not digital circuit. You need to learn custom IC design fundamentals for that.
This book will help you:
Amazon.com: CMOS Circuit Design, Layout, and Simulation, Second Edition (9780471700555): R. Jacob Baker: Books

 

[embeddedlover]

Yes, it is not a digital circuit... but i wanted to know how to proceed with Analog circuit design in ASIC...

For digital design we have VHDL/Verilog where by we will be creating a verilog netlist...n so on

Likewise i wanted to know the procedure for Analog circuits design....

 

[rca]

vhdl/verilog create verilog netlist but you could never generate a opamp., verilog netlist only instantiate cell, which could be amp or waht you want.

 

[embeddedlover]

I browsed several articles and found that Analog design is not an easy process....

I am thinking of proceding this way...

1. Create a schematic.
2. Use some simulator to verify the performance (like multisim where opamp libraries are present)
3. Create a netlist from the finalized schematic....
4. convert the generated netlist to verilog netlist...

Does this work for me?
What kind of simulator & schematic capture i have to use for this?

 

[FvM]

2. Use some simulator to verify the performance (like multisim where opamp libraries are present)

A analog simulator can be used, but it doesn't provide opamp libraries for you. You have to simulate the transistor level circuit, using transistor models for your involved ASIC process. For a mixed signal process, an ASIC vendor most likely has some libraries of analog macrocells. Even in a mixed signal process, you shouldn't overestimate the achievable OP performance, particularly in terms of device matching respectively offset voltages. Also the properties of available pads and their protection circuits may considerably restrict the analog design capabilities.

4. convert the generated netlist to verilog netlist...

The analog ASIC part can't be described in a Verilog netlist. The transistor level circuit has to be processed in the IC design tool.

 

[rca]

just to complicate.
the analog tools can generate a verilog netlist but this one will instantiate module that have transisitor for your opamp, and as describe by FvM, you can not used this kind of netlist in "digital" backend flow, like Encounter/Astro/Magma...

 

[embeddedlover]

Useful info rca & FvM...

I have a basic schematic of my requirement...Example assuming schematic as having a single opamp(Ex:LM741)....
Now where i have to start from....?
what kind of simulator should i go for...?
I thought multisim will work for me as it has as analog libraries especially opamp libraries...

Are there any simulators available from ASIC vendors for mixed signal approach....?

 

[FvM]

What kind of ASIC process you're talking about? I guess it's rather CMOS than bipolar, so good old 741 won't be feasible.

SPICE simulators like Multisim have libraries with macro models of popular devices, no transistor level libraries suited for IC design.

Mixed signal IC designers mostly use tools like Cadence Virtuoso for implementation and simulation.

 

[embeddedlover]

Can i start my analog designs with Cadence virtuoso?
Are there inbuilt libraries of opamp available in it?
Is cadence virtuoso starting point for mixed signal ASIC designs?

Any tools other than cadence virtuoso?

 

[rob1012]

Cadence Virtuoso offers a powerful design/simulation tool both for analog and digital ASIC design. yes you can design schematic via schematic editor, simulate via analog design environment or spectre circuit simulator. there are basc libraries you can find in it. but, for a realistic model you need to have a spice model of a particular process you want to design your op-amp under. Cadence AMS designer is the starting point for mixed-signal ASIC designs.

You can try Synopsis' Discovery AMS design tool as an alternative.

hope this helps.