how to implement MultI -Vt designs

[sudheerprasad]

hi,
regarding multi vt designs,should we design the cells in standard cell lib with multi vts,say a 3i /p nand gate,two nmos are having lower vt and third one higher vt, or is it some something dealt with the tools,like a multi vdd design can be done during backend stage

 

[arjun1110]

Hi Sudheerprasad,

Leakage optimization is one of the low power implementation technique. And when you want use this technique during implementation process, your standard library should have both types of cells i.e High-vt and Low-vt.

>>a 3i /p nand gate,two nmos are having lower vt and third one higher vt,
It is not the way you understand, You will have two seperate nand gate (All cells in the library)with High-vt and Low-vt.

High-vt cells will have less leakage,more delay.
Low-vt cells will have more leakage,less delay.

Hope you are clear now.

Regards,