How to implement fast adder in xilinx FPGA?

[mhytr]

fpga fast adder

I found that a 16bit adder in Spartan3 FPGA have a delay of about 6ns.
But the embeded 18bit multiplier in Spartan3 FPGA have a delay of only 8 ns.
I want to do a multiplication followed by a addition in 1 clock time,so i need to reduuce the delay of adder.
Can anybody give me some advice? Thanks

 

[echo47]

fast adder

Those ns numbers seem too slow. How fast do you need it to go? Which speed version chip are you using? How many bits of the multiplier are you using? Normally you want to rearrange the arithmetic to use pipelining. If you show us example test code that can be compiled, maybe someone can suggest improvement.

 

[bibo1978]

very fast adder

use a parallel pipelined multiplier with an adder, this way you will not loose your throughput, i.e. you will get a result each clock cycle but you will have some latency.

 

[Johnson]

fast 16 bit fpga adder

I suppose that basedon your const. synthesis tool will choose the best one, so that it is better to work around it on synthesis const. However big addre always has speed problem!