How to implement ESD snapback model in SOI

[Kelvintlai]

In CMOS bulk technology, snapback on ESD transistor is normally model by a MOS in parallel with BJT, plus avalanche trigger current. How do we model it on SOI transistor?

 

[dick_freebird]

Similarly, in my experience. I've always used a diode model
with the forward params dummied out and the reverse
params fitted to TLP data. What kind of SOI affects the
BJT component - how deep the S/D junctions goes to
base area, L to base width / beta. SOI parasitic BJTs can
be hard to exercise well enough to get good parameter
extraction, Rb is often huge (to the probes) but tiny when
you're talking about the trigger path (impact ionization or
avalanche, it's right there). The body tie resistance should
be extrinsically modeled, because of this (Rb being
different depending on what you're looking at). What I
have never been able to model nicely is the actual snapping-
back to the lower-than-breakdown holding voltage. I think
that probably wants some veriloga.