omara007
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Hi folks
I am trying to implement a division function on Xilinx V4. What I know is that only multipliers are built in. In other words, it's unlike ASIC in which I can pull a DW component for the multiplier.
Does anyone have a work around designing dividers in FPGAs without having to actually code up a divider by hand ?
I am trying to implement a division function on Xilinx V4. What I know is that only multipliers are built in. In other words, it's unlike ASIC in which I can pull a DW component for the multiplier.
Does anyone have a work around designing dividers in FPGAs without having to actually code up a divider by hand ?