Hi all,
I am work on DFT for a design with three clock domains. Could anyone tell me how to implement DFT with singe scan clock? Do I need to add mux to bypass the clocks of the other two clock domains? And drive clock pins of all the registers with the single scan clock?
Thanks a lot.
Hi ,
Eventhough you convert all DFF -> SDFF of all chains ,if there are multiple clock domain flops in a chain ,then to handle this clock muxing is done .Also if the paritcular clock is not handled from the top level & its generated internally .Then test_clk has to be muxed with func clock.
When mucking around with the clocks in multi-clock domain chips you are likely to have timing problems. If you rebalance the clock tree so that one clock pin can drive all FFs in test mode you will effect performance in functional mode. I suggest that you give each clock domain it's own clock pin for test mode. That will have the least impact on your clock tree.