How to implement DELAY in a circuit?

[isaacnewton]

Dear All,

The attached circuit diagram is a Multiphase Clock Generator. This is for an A/D converter. In this circuit, there is a DELAY block which is highlighted. Can somebody tell me a simple way to implement the DELAY block? Thank you very much.

 

[mike_bihan]

use inverter chains.

 

[Hughes]

The delay cell can be one or more cmos buffers with small w/l ratios (w<l).

 

[arthur]

Because of the gate delay is too short, we generally use the RC to implement delay line.
R
^^^^----
|
= C
|
===
=

 

[echo47]

arthur, highlight your text and press the "Code" button, like this:

     R
    ^^^^----
         |
         =  C
         |
        ===
         =

 

[radiohead]

For large delay you will need large R and/or C. This mean a lot of die area = expensive. This is why invertor chain is the preferred solution. Use small W/L, and add as many stages as needed. You can even trim delay by changing the bias current.

 

[cetc1525]

I think the time in AD is very small.just use inverters.

 

[StevenL]

I myself use inverter chains too in AD design.

I have a question though, has anybody ever experienced problems from too short or too long delays due to process variations?

 

[qy79]

more invertors more clock jitter due to supply noise

 

[qutang]

we can use some f-f to reduce jitter.

 

[surianova]

Try to use 2 inverters with with small W/L ratio to delay the circuit. If the the delay still not enough, can put a capacitor between the inverter to genarate more delay. You can use mosfet capacitor because of its smaller size.

 

[piao]

maybe you can also add capacittance between the inverter.

 

[cetc1525]

a capacitor need large area.

 

[devrimaksin]

You can use gate oxide of a transistor for implementing the cap, the solution is RC

 

[Teddy]

You can try to use "current starved" delay line - similar to vco ring osc.
Then you can modify your delay by changing the bias. Generaly you would get more resolution and quite a bit of range.

 

[zmliu]

The commonest way is inverter chain.

 

[fragment]

Inverter chains have more predictable delay then RC-line

 

[leo_o2]

In my design, a huge variation harass me a lot. Any idea about it?