How to implement DCT in VHDL?

[dianacgil]

Hello...
I'm working in my final project about video coding. I'm working with a HW/SW codesign methodology (HW: VHDL --> Cyclone FPGA / SW: C --> Nios Altera processor). I'm trying to develop the principal modules in a Cyclone, such as DCT, Q, Q-1, IDCT...
Until now, I've been thinking in DCT (Chen's algorithm). Do you have any idea about how to implement DCT in VHDL? I have an algorithm's flow but I don't know how to translate it to VHDL. :?:
Thanks a lot.

 

[swahlah]

Re: Help video codec

Hi,

Your question is ambiguous. You need to elaborate your problem and explain the exact requirements of your problem.

Specifically you need to think in detail about the interfaces(input/output) and the timing requirements(real time/ off-line solutions).

Once you have decided all that then you can proceed to coding. Since your whole implementation depends upon the specifications therefore you need to elaborate the requirements of your system quite more explicitly. This thing will describe the type of your core modules(e.g. adder, multiplier). If you have the proper butterfly of your DCt algorithm then you can simply connect your core modules to get the results of DCT. So the major problem in hardware implementations is the sytem requirements.


Sincerely,

 

[sunroof]

Help video codec

Try to think about the whole design first, find out input/output requirements, and decide how to spli the design to modules, then, give as much as possible definitations of each module, see whether you need and how to modify the algorithm to fit the hardware device.

Also, you may want to check google newsgroups, such as VHDL, to find out some hints.

good luck.

 

[dianacgil]

Re: Help video codec

Ok.
I've been trying to implement DCT-2D in VHDL. I'm working with Chen's algorithm, but now the problem is that my design is huge: 2500 LEs approx. (using a Cyclone). The basic idea is to implement 16 multiplications and 26 additions in a concurrent form, but the results tell me that it's inefficient in terms of logic resources. Therefore, it's much better thinking in reusing 1 adder and 1 multiplier, but doing only 16 mult. and 26 add., instead of implementing 16 multipliers and 16 adders at the same time. How can I do this?
Any help?

Thanks!

 

[eDance]

Help video codec

I suggest you use a dedicate video codec, such as ADV202 from ADI. It's a jpeg2000 processor compatible with many standard digital video format.
If you insist on using PLD, a video processing IP core may be helpful for you, I remember it's available from opencore.org. Good luck.

 

[swahlah]

Re: Help video codec

What really you can do is to first simplify the butterfly as per your underlying hardware architecture using the optimized arithmetic logic. And then you can implement the fast multipliers and fast adders which can take fewer clock cycles and also efficient in context of space. For fast Multipliers and adders you can refere to the book of ISRAEL KOREN, It contains lots of fast arithmetic algorithms and definitly useful for you. In context of number of multiplier and adder i will suggest you to reuse the components. But you have to choose an appropriate number of multiplier and adders...................
Otherwise DCT is not a difficult algorithm to implement.
Regards.