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How to implement checksum in VHDL?

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Oana

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Hello everyone,

Anybody can tell me how can i implement a checksum in vhdl.
Thanks!!
Oana
 

childs

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vhdl checksum

checksum is somehow different from CRC....

procedure for checksum is:
1. slice the data into 16-bit slices
2. sums up the 16-bit data start from the 1st, if overflow, add 1 into the sum
3. if the remaining data has only 8-bit, pad x"00" to its end to become 16-bit

I might not sound it clear, below is part of example of vhdl code, this is not compilable, just for quick understanding of checksum calculation:

in16b = unsigned(15 downto 0)
sum = unsigned(16 downto 0), initial = (OTHERS => '0')
result = std_logic_vector(15 downto 0)
p.s: when examining checksum, result = x"FFFF" means correct; when generating checksum, result = calculated checksum

IF (cs = '1') THEN
sum := sum + in16b;
IF (sum(16) = '1') THEN
sum := '0' & sum(15 downto 0) + "1";
END IF;
END IF;
IF (finsih = '1') THEN
FOR i IN 0 TO 15 LOOP
result(i) <= NOT(std_logic(sum(i)));
END LOOP;
END IF;
 

Oana

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crc in vhdl

Thanks alot childs!!
This helps me.
And if it were to implement CRC, how would that look?:D
I looked for the CRC algorithm but i coudn't find a clear answer....

Thanks!!
 

childs

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vhdl crc

link provided by benradu have lot of information about code for CRC...

btw I suppose u meant to CRC-32 that is used for Ethernet. According to 802.3 standard specification, section 3.2.8 - Frame Chksum Sequence (FCS) field:

".....The encoding is defined by the following generating polynomial.
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Mathematically, the CRC value corresponding to a given frame is defined by the following procedure:
a) The first 32 bits of the frame are complemented.
b) The n bits of the frame are then considered to be the coefficients of a polynomial M(x) of degree n–1.
(The first bit of the Destination Address field corresponds to the x(n–1) term and the last bit of the data field corresponds to the x0 term.)
c) M(x) is multiplied by x32 and divided by G(x), producing a remainder R(x) of degree ≤31.
d) The coefficients of R(x) are considered to be a 32-bit sequence.
e) The bit sequence is complemented and the result is the CRC.
The 32 bits of the CRC value are placed in the frame check sequence field so that the x31 term is the leftmost bit of the first octet, and the x0 term is the right most bit of the last octet. (The bits of the CRC are thus transmitted in the order x31, 30,…, x1, x0.) See reference [B32].

Hope you can get clearer picture....
 

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