harsha44
Newbie level 3
Hi ppl,
I need to design an all digital PLL (ADPLL) to be incorporated into an SDR to generate the necessary clk signals. I need to know if its possible to implement an all-digital design on an FPGA board since the Digitally controlled oscillator(DCO) requires a high frequency clock to be fed to it. However, i need to generate the following signals using only a single 100MHz clock:
200MHz
300MHz
42.8MHz
21.4MHz
10.&MHz
0.1MHz
Since the DCO needs another clock signal to function , im in a real fix here since i have only one signal available to me : the reference frequency 100MHz.
Please suggest some way around this or any architecture suitable for FPGA design.
I need to design an all digital PLL (ADPLL) to be incorporated into an SDR to generate the necessary clk signals. I need to know if its possible to implement an all-digital design on an FPGA board since the Digitally controlled oscillator(DCO) requires a high frequency clock to be fed to it. However, i need to generate the following signals using only a single 100MHz clock:
200MHz
300MHz
42.8MHz
21.4MHz
10.&MHz
0.1MHz
Since the DCO needs another clock signal to function , im in a real fix here since i have only one signal available to me : the reference frequency 100MHz.
Please suggest some way around this or any architecture suitable for FPGA design.