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How to Implement a repetitive design?

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dw_man

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I have a RTL design (from VHDL) which has been synthesized and routed using IC Compiler. I want to include multiple instances of this design which has already been routed successfully.

Rather than including a top level VHDL module which instantiates multiple instances and then routes the entire design, is it possible to just use the individual design as a 'black-box' and then connect the inputs and outputs to each other, meaning the same design will not have to routed over and over multiple times?
 

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