How to implement a PLL lock detector?

[DZC]

pll lock detector

Is there any common used method?

 

[E-design]

pll lock detection

Do you want just a indication when lock is achieved, like a circuit with a LED?

 

[taotaohai]

lock detector

start from the point before VCO,the voltage is a fine detector point.

 

[zorro]

up down signal pll

Hi,

A good method is to use a second phase detector (PD) that compares the phase of the incoming signal with the VCO shifted 90 degrees.

When locked, the (filtered) output of this second PD is a DC.
Without input signal, the output is zero (or noise if the input is just noise).
When unlocked, the output oscilates with zero mean (no DC).
So, a low-pass filter followed by a threshold comparator gives the lock indication.

Regards

Z

 

[rania_hassan]

how pll locked

Hi, you can use XOR for the Up and Down signals and take the out after certain delay time
if we have lock, the Up and Down signal are the same
Best regards,
Rania

 

[rfsystem]

pll mit xor

As Rania point out use an XOR of UP and DOWN than make an RC-lowpass of the XOR ouput and compare to fraction of logic supply. Locking means to stay within a phase difference which is the fraction of the lowpass filtered XOR.

 

[zoujunjx]

lock detect pfd up down

I also need a pll lock detector, could anyone provider some papers or some schematic diagrams? Many thanks in advance!

To rania_hassan,
Up and Down signals could not be exactly same in practice. If using XOR gate, it might generate wrong message. How to avoid it?

To rfsystem
What's mean the fraction of digital supply? Do you mean that the filtered outpuf of XOR is compared to a reference voltage, which is e.g. 0.5*VDD ? Please correct me if I misunderstood.

 

[rania_hassan]

pll lock detector

To zoujunjx
Up and Down signals are exactly the same if you use PFD