how to implement a DFF in verilog?

[newcpu]

verilog dff

Hi,
I want to implement a DFF in verilog. And I know the method in the following:
always@(posedge clk)
begin
if(EN)
q<=d;
else
q<=q;
end
Could we avoid the"else q<=q; q<=q; " with other method?
Best Regards,
newcpu

 

[maksya]

verilog dff with enable

Yes, we could. It is not necessary to use this string in your code. Synthesizer understand this code as a D flip flop:

module D_flipflop (d, q, clock, enable);

input d;
input clock;
input enable;

output q;

reg q;

always @ (posedge clock) begin if (enable) q = d; end

endmodule

 

[spauls]

Is enable really required ?

 

[avimit]

No, Enable is not required. you can write

always @ (posedge clk) q<=d;

 

[venu pradeepa]

dude , try this :

always @ (posedge clk )
begin
if (reset)
q<=1'b0;
else
q<=d;
end

Added after 1 minutes:

dude , try this :

always @ (posedge clk )
begin
if (reset)
q<=1'b0;
else
q<=d;
end

 

[barkha]

https://www.asic-world.com/examples/verilog/d_ff.html
Link is good