How to implement a big rom ?

[madalin1990]

I want to display an 800x600 picture using a vga controller.I have used a rather "barbaric" method to implement the ROM:using a matlab script I generated 480000 times:

 assign mem [address] = pixel_value

Unsurprisingly synthesizing is taking forever to finish.
So does someone have an idea of how to implement this memory more efficiently?

 

[FvM]

There are two problems involved with your question:
- suitable methods to enter ROM data to HDL designs
- how to enforce inference of FPGA internal memory for the ROM (provided the FPGA has built-in sufficient memory capacity, which should be checked as a first step.

For the first point, Verilog has the option to read binary and hex files with systems function $readmemb() and $readmemh().

For the second point, the way how the memory is accessed in your code matters. Internally memory is usually synchronoius, it must be read under a clock edge sensitive condition, and you can only read one location for a clock cycle (or possibly two with dual-port memory).

 

[madalin1990]

Is $readmemb() and $readmemh() synthesizable?

 

[ads_ee]

Based on two web sites they are synthesizable if the tool supports it, which looks like the case for Xilinx and Altera
http://forums.xilinx.com/t5/Simulat...eadmemh-or-readmemb-synthesizable/td-p/149070
http://stackoverflow.com/questions/4321067/is-readmem-synthesizable-in-verilog

 

[permute]

800x600x8 is 38400000 bits, or 105 36kbit BRAMs. Make sure the FPGA has enough resources. Once you run out of BRAMs, the tools will try distributed rams and registers. At that point it will typically run for a long time and then tell you it failed to implement the design due to overmapping. (or it will work, but use most of the FPGA)

you likely want to start with smaller images, or store the frame in external memories.

 

[madalin1990]

thank you for your replies.I will try to implement a smaller picture to see if this works