There are two problems involved with your question:
- suitable methods to enter ROM data to HDL designs
- how to enforce inference of FPGA internal memory for the ROM (provided the FPGA has built-in sufficient memory capacity, which should be checked as a first step.
For the first point, Verilog has the option to read binary and hex files with systems function $readmemb() and $readmemh().
For the second point, the way how the memory is accessed in your code matters. Internally memory is usually synchronoius, it must be read under a clock edge sensitive condition, and you can only read one location for a clock cycle (or possibly two with dual-port memory).