How to handle this case in DC synthesis?

[mic_huhu]

Hi,all

How to handle this case?

My design has a system asychoronous reset ,and only one submodule has a module asychoronous reset from another module. other submodules share this system asychorounous reset.

How to handle the submodule asy reset in DC synthesis?

and whether this design has a disadvantage?


Thanks

Johnny

 

[ami]

one submodule has a module asychoronous reset from another module

Hi,
It is OK, but you should take care these below things:
1. In Scan_mode, all FF should be reset by the PIN MASTER RESET. so, you need to have a MUX (select by SCAN_TEST signal) to mux the internal reset with the MASTER RESET before using in your sub-module.

2. In DC script, set_false_path from the output of the MUX

Rgrds
AMi

 

[mic_huhu]

Hi,

when I need do it ? Modify RTL before synthesis or DFT after synthesis?

Johnny

 

[ami]

Hi,
Do it in your current RTL. and another notice while synthesis: all CLOCK_MUX and SCAN_MUX cells should be set dont_touch attribute.
the output of the RESET_MUX (all reset and clock nets as well) should be set_dont_touch_network in DC script.
Rgrds

 

[anjali]

Hi,

when I need do it ? Modify RTL before synthesis or DFT after synthesis?

Johnny

no need to modify RTL before synthesis. do synthesis in your way.

while inserting DFT, we can direct the tool to insert scan_muxes at the reset input of the submodule, such that in scan mode submodule will be resetted by master reset, in functional mode, it uses internally generated reset.

the constraints are,
set_dft_configuration -autofix
set_autofix_configuration -async_fix fix_muxes

2nd constraint may not have exact options. please refer sold. but idea is correct.

 

[ami]

Hi,

when I need do it ? Modify RTL before synthesis or DFT after synthesis?

Johnny

no need to modify RTL before synthesis. do synthesis in your way.

while inserting DFT, we can direct the tool to insert scan_muxes at the reset input of the submodule, such that in scan mode submodule will be resetted by master reset, in functional mode, it uses internally generated reset.

the constraints are,
set_dft_configuration -autofix
set_autofix_configuration -async_fix fix_muxes

2nd constraint may not have exact options. please refer sold. but idea is correct.

Just have a question on this, how does the DC recognize which pin is MASTER_RESET?

I haven't used this method before because I think these special type of MUXs should be taken care by hand.

 

[anjali]

first thing is,
reset can be synchronous or asynchronous

in the case of synvhronous reset, there are no issues or problrms in DFT insertion.
in the case of async reset, while inserting DFT, we need to take care that the async reset will not interrupt the scan process. so we will use mux, such that
when se = 0 , that async reset goes to the flop
when se = 1, any sync signal or synchronized version of async reset should reach the flop.
this can be done by the constraint,
set_signal_type test_async reset

the above explanation is if the reset is master_reset ( input)
now one more case is if the reset is internally generated one. this also can be connected to the flop as sync or async.
there is no problem if it is connected as sync.
in the case of async, we can use the following,
set_dft_configuration -autofix
set_autofix_configuration -async_fix fix_muxes

 

[ami]

Hi friends,
1. Fix RTL and then synthesis, we can do the same simulation on both RTL and gate-level.
2. It is not wise to let DC to handle these MUX during DFT_fix - they are not DFT and must be done in synthesis. All pecial cell & net such as these above things should be take care by hand in RTL(epescially in hierrachical synthesis flow).

Rgrds

 

[mic_huhu]

Hi, Ami and Anjali,

Thank both you very much for helps.

I think both you are right. I want ask for you two questions:

1: When I set false path for submodule reset (async reset ), whether means DC don't handle it and leave it to Layout engineer ? and How to do the layout engineer ?

2: If I don't set false path on the submoudle async reset, and Dc will treat it as a sync reset . what are the result ? I think those FF with asyn reset will can't be inserted into the scan chains . How about others (such as function, performance ) ?

Thanks

Johnny

 

[ami]

Hi, Ami and Anjali,

Thank both you very much for helps.

I think both you are right. I want ask for you two questions:

1: When I set false path for submodule reset (async reset ), whether means DC don't handle it and leave it to Layout engineer ? and How to do the layout engineer ?

2: If I don't set false path on the submoudle async reset, and Dc will treat it as a sync reset . what are the result ? I think those FF with asyn reset will can't be inserted into the scan chains . How about others (such as function, performance ) ?

Thanks

Johnny

hi,
let me try to answer your questions
1. set_false_path just let DC know that this path is false_path, and DC will ignore its timing( DC will not try insert anything or optimize this path to meet the design constraint). RESET path should be also set as dont_touch_network (as well as CLOCK) - all reset path will be inserted clock_root then(layout).
2. I suppose that your design is synchronus design, is it right? and the FFs you use should be synchronus-FF (sync-reset) - OK? if so, just set these reset paths as false_path and dont_touch_network, they will be taken care in the back end process(ctsroot expand).
hope this help
AMi

 

[mic_huhu]

Hi,ami,

Do U meaning sync_design should set_false_path on sync reset ?

In my opnion, set_flase_path on asyn reset and treat syn reset as an normal input.

 

[ami]

hi,
yes, in syn_design - sync-reset should not set as fasle_path. but in design flow, in synthesis, you should ignore its timing. After syntheis, reset_path will be taken care(insert buffer tree).

 

[appleleaf]

This reset style is fine, and there could be more complex reset as well.
The DFT autofix will handle the reset problem automatically. Or you can add Scan friendly structure manually.

 

[anjali]

DFT autofix can handle. i feel.