how to handle synopsys DW_mac in FPGA?

[quan228228]

In my design, we use a DW_mac of synopsys. In FPGA, how to treat it ?

I found, the result of FPGA is wrong. I have some doubt:

1. is the DW_mac verilog file synthesisable in FPGA
2. the synplify tool doesn't report any error about this module, Why the test result is wrong. for example, -1 x -1 = -1 .


Thanks!

David

 

[firewire2035]

#1 sounds like you are explicitly inferring a DW, any reason for doing that? You can use pragmas for inferring specific ASIC implementation, and keep your RTL technology independent.


#2 did you have the signs extended properly?

 

[quan228228]

the DW_MAC file is like this.


module DW02_mac
(A, B, C, TC, MAC);

parameter A_width=8;
parameter B_width=8;

// port list declaration in order
input [ A_width- 1: 0] A;
input [ B_width- 1: 0] B;
input [ A_width+B_width- 1: 0] C;
input TC;
output [ A_width+B_width- 1: 0] MAC; reg [ A_width+B_width- 1: 0] MAC;

function [ A_width+B_width- 1: 0] signed_mult;
input [ A_width- 1: 0] A;
input [ B_width- 1: 0] B;
reg [ A_width- 1: 0] a1;
reg [ B_width- 1: 0] b1;
reg [ A_width+B_width- 1: 0] c1;
begin
// synopsys synthesis_off
if ( (A[A_width-1] === 1'bx || B[B_width-1] === 1'bx) ) begin
signed_mult = {A_width+B_width{1'bx}};
end else
// synopsys synthesis_on
begin
if (A[A_width-1] === 1'b1)
a1 = -A;
else
a1 = A;
if (B[B_width-1] === 1'b1)
b1 = -B;
else
b1 = B;
c1 = a1*b1;
if (A[A_width-1] !== B[B_width-1])
signed_mult = -c1;
else
signed_mult = c1;
end
end
endfunction

always begin
if ( TC === 1'b1 ) begin // signed multiplication
MAC <= signed_mult(A,B)+C;
end else begin
MAC <= A*B+C;
end // if
@(TC or A or B or C);
end // process

endmodule

 

[firewire2035]

TC === 1'b1 ?

 

[quan228228]

TC === 1'b1 ?

Well, the tool synplify can automatically correct it with (TC == 1'B1). So, no problem with this.

I wonder if the statement "function" is synthesisable. and the synopsys comments is right for FPGA tool.

David

 

[firewire2035]

function is synthesizable.

 

[samirkag]

I think you might just have violated a non disclosure agreement by copy-pasting the dw code...

the DW_MAC file is like this.


module DW02_mac
(A, B, C, TC, MAC);

parameter A_width=8;
parameter B_width=8;

// port list declaration in order
input [ A_width- 1: 0] A;
input [ B_width- 1: 0] B;
input [ A_width+B_width- 1: 0] C;
input TC;
output [ A_width+B_width- 1: 0] MAC; reg [ A_width+B_width- 1: 0] MAC;

function [ A_width+B_width- 1: 0] signed_mult;
input [ A_width- 1: 0] A;
input [ B_width- 1: 0] B;
reg [ A_width- 1: 0] a1;
reg [ B_width- 1: 0] b1;
reg [ A_width+B_width- 1: 0] c1;
begin
// synopsys synthesis_off
if ( (A[A_width-1] === 1'bx || B[B_width-1] === 1'bx) ) begin
signed_mult = {A_width+B_width{1'bx}};
end else
// synopsys synthesis_on
begin
if (A[A_width-1] === 1'b1)
a1 = -A;
else
a1 = A;
if (B[B_width-1] === 1'b1)
b1 = -B;
else
b1 = B;
c1 = a1*b1;
if (A[A_width-1] !== B[B_width-1])
signed_mult = -c1;
else
signed_mult = c1;
end
end
endfunction

always begin
if ( TC === 1'b1 ) begin // signed multiplication
MAC <= signed_mult(A,B)+C;
end else begin
MAC <= A*B+C;
end // if
@(TC or A or B or C);
end // process

endmodule

 

[fpga_asic_designer]

David,

I also got this problem while doing FPGA. We use synopsys DW FIFO in our ASIC. It gives problem in FPGA. The verilog code is only a behavior model and cannot be synthesized (thats' why whenever you use it, you must tell DCshell where to load the synopsys DW). We end up designing a separate FIFO that can be synthesized for FPGA. Our design must be ugly than Synopsys, but it's working...

Another option is to synthesize the DW from synopsys, get the synthesized netlist and dump that netlist into FPGA. You can easily map the gates used in DW into behavior model... (not sure if there is any legal problem using Synopsys this way... )

If you try to use the synthesized netlist, let me know if it's working or not.

Ke

In my design, we use a DW_mac of synopsys. In FPGA, how to treat it ?

I found, the result of FPGA is wrong. I have some doubt:

1. is the DW_mac verilog file synthesisable in FPGA
2. the synplify tool doesn't report any error about this module, Why the test result is wrong. for example, -1 x -1 = -1 .


Thanks!

David

 

[samuraign]

Will it be possible to replace it with Megawizard Macro.